Zhang Rui 0c2ddedd8b intel_rapl: support two power limits for every RAPL domain ... RAPL MSR interface supports 2 power limits for package domain, and 1 power limit for other domains, while RAPL MMIO interface supports 2 power limits for both package and dram domains. And when 2 power limits are supported, the FW_LOCK bit is in bit 63 of the register, instead of bit 31. Remove the assumption that only pakcage domain supports 2 power limits. And allow the RAPL interface driver to specify the number of power limits supported, for every single RAPL domain it owns.. Reviewed-by: Pandruvada, Srinivas <srinivas.pandruvada@intel.com> Tested-by: Pandruvada, Srinivas <srinivas.pandruvada@intel.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>		2019-07-11 15:08:58 +02:00
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idle_inject.c
intel_rapl_common.c	intel_rapl: support two power limits for every RAPL domain	2019-07-11 15:08:58 +02:00
intel_rapl_msr.c	intel_rapl: support two power limits for every RAPL domain	2019-07-11 15:08:58 +02:00
Kconfig	intel_rapl: abstract RAPL common code	2019-07-11 15:08:58 +02:00
Makefile	intel_rapl: abstract RAPL common code	2019-07-11 15:08:58 +02:00
powercap_sys.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 309	2019-06-05 17:37:04 +02:00