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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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0be1621a74
Most processor modules (e.g., DSP, IVA, IPU) on OMAPs can be reset under the control of the PRM. This patch adds an API for this purpose for OMAP4 devices: int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift); int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); This API is intended to be used only by the hwmod code - a subsequent patch will add that support to hwmod. This patch is a collaboration between Benoît Cousson <b-cousson@ti.com> and Paul Walmsley <paul@pwsan.com>. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com>
117 lines
3.7 KiB
C
117 lines
3.7 KiB
C
/*
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* OMAP4 PRM module functions
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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* Benoît Cousson
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <plat/common.h>
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#include <plat/cpu.h>
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#include <plat/prcm.h>
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#include "prm.h"
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#include "prm-regbits-44xx.h"
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/*
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* Address offset (in bytes) between the reset control and the reset
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* status registers: 4 bytes on OMAP4
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*/
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#define OMAP4_RST_CTRL_ST_OFFSET 4
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/**
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* omap4_prm_is_hardreset_asserted - read the HW reset line state of
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* submodules contained in the hwmod module
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* @rstctrl_reg: RM_RSTCTRL register address for this module
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* @shift: register bit shift corresponding to the reset line to check
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*
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* Returns 1 if the (sub)module hardreset line is currently asserted,
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* 0 if the (sub)module hardreset line is not currently asserted, or
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* -EINVAL upon parameter error.
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*/
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int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift)
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{
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if (!cpu_is_omap44xx() || !rstctrl_reg)
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return -EINVAL;
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return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift));
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}
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/**
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* omap4_prm_assert_hardreset - assert the HW reset line of a submodule
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* @rstctrl_reg: RM_RSTCTRL register address for this module
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* @shift: register bit shift corresponding to the reset line to assert
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*
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* Some IPs like dsp, ipu or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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* IP. These modules may have multiple hard-reset lines that reset
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* different 'submodules' inside the IP block. This function will
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* place the submodule into reset. Returns 0 upon success or -EINVAL
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* upon an argument error.
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*/
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int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift)
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{
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u32 mask;
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if (!cpu_is_omap44xx() || !rstctrl_reg)
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return -EINVAL;
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mask = 1 << shift;
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omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg);
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return 0;
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}
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/**
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* omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait
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* @rstctrl_reg: RM_RSTCTRL register address for this module
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* @shift: register bit shift corresponding to the reset line to deassert
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*
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* Some IPs like dsp, ipu or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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* IP. These modules may have multiple hard-reset lines that reset
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* different 'submodules' inside the IP block. This function will
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* take the submodule out of reset and wait until the PRCM indicates
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* that the reset has completed before returning. Returns 0 upon success or
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* -EINVAL upon an argument error, -EEXIST if the submodule was already out
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* of reset, or -EBUSY if the submodule did not exit reset promptly.
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*/
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int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift)
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{
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u32 mask;
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void __iomem *rstst_reg;
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int c;
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if (!cpu_is_omap44xx() || !rstctrl_reg)
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return -EINVAL;
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rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET;
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mask = 1 << shift;
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/* Check the current status to avoid de-asserting the line twice */
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if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0)
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return -EEXIST;
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/* Clear the reset status by writing 1 to the status bit */
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omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg);
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/* de-assert the reset control line */
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omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg);
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/* wait the status to be set */
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omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask),
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MAX_MODULE_HARDRESET_WAIT, c);
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return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
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}
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