mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
6354a06cba
This reverts commit 6f2dea1f5f.
Without accurate cpu regulators being set for boards this will wreak havoc
when cpufreq-dt begins to set new frequencies without adjusting the core
frequency.
Additionally the rk3368 has an unsolved issue in that it has two separate
cpu clusters with separate clock lines but only one cpu supply regulator
for both clusters, which causes even more problems.
While it seems that originally only one cluster was supposed to be active
at a time (big or little), talking with real users of the hardware
revealed that having all 8 cores accessible at 1.2GHz max is way more
liked than having 4 cores at 1.5GHz max. Such an approach needs changes
to cpufreq and/or opp though to control the two separate clock lines when
setting both clusters to the same frequencies.
In any case, having the OPPs in the dts at this point in time is
undesireable, so remove them again for now.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
1225 lines
31 KiB
Plaintext
1225 lines
31 KiB
Plaintext
/*
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* Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/rk3368-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "rockchip,rk3368";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &gmac;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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spi0 = &spi0;
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spi1 = &spi1;
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spi2 = &spi2;
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu_b0>;
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};
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core1 {
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cpu = <&cpu_b1>;
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};
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core2 {
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cpu = <&cpu_b2>;
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};
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core3 {
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cpu = <&cpu_b3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu_l0>;
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};
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core1 {
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cpu = <&cpu_l1>;
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};
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core2 {
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cpu = <&cpu_l2>;
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};
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core3 {
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cpu = <&cpu_l3>;
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};
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};
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};
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cpu_l0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu_l1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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cpu_l2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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};
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cpu_l3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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};
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cpu_b0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu_b1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x101>;
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enable-method = "psci";
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};
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cpu_b2: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x102>;
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enable-method = "psci";
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};
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cpu_b3: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x103>;
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enable-method = "psci";
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};
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dmac_peri: dma-controller@ff250000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xff250000 0x0 0x4000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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clocks = <&cru ACLK_DMAC_PERI>;
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clock-names = "apb_pclk";
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};
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dmac_bus: dma-controller@ff600000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xff600000 0x0 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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clocks = <&cru ACLK_DMAC_BUS>;
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clock-names = "apb_pclk";
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};
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};
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arm-pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
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<&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
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<&cpu_b2>, <&cpu_b3>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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sdmmc: dwmmc@ff0c0000 {
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compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xff0c0000 0x0 0x4000>;
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max-frequency = <150000000>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&cru SRST_MMC0>;
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reset-names = "reset";
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status = "disabled";
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};
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sdio0: dwmmc@ff0d0000 {
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compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xff0d0000 0x0 0x4000>;
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max-frequency = <150000000>;
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clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
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<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
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clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&cru SRST_SDIO0>;
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reset-names = "reset";
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status = "disabled";
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};
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emmc: dwmmc@ff0f0000 {
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compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xff0f0000 0x0 0x4000>;
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max-frequency = <150000000>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&cru SRST_EMMC>;
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reset-names = "reset";
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status = "disabled";
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};
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saradc: saradc@ff100000 {
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compatible = "rockchip,saradc";
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reg = <0x0 0xff100000 0x0 0x100>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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#io-channel-cells = <1>;
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clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
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clock-names = "saradc", "apb_pclk";
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resets = <&cru SRST_SARADC>;
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reset-names = "saradc-apb";
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status = "disabled";
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};
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spi0: spi@ff110000 {
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compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff110000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@ff120000 {
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compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff120000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@ff130000 {
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compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff130000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@ff140000 {
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compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
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reg = <0x0 0xff140000 0x0 0x1000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C2>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_xfer>;
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status = "disabled";
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};
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i2c3: i2c@ff150000 {
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compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
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reg = <0x0 0xff150000 0x0 0x1000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C3>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_xfer>;
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status = "disabled";
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};
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i2c4: i2c@ff160000 {
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compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
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reg = <0x0 0xff160000 0x0 0x1000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C4>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_xfer>;
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status = "disabled";
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};
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i2c5: i2c@ff170000 {
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compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
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reg = <0x0 0xff170000 0x0 0x1000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C5>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_xfer>;
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status = "disabled";
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};
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uart0: serial@ff180000 {
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compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff180000 0x0 0x100>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart1: serial@ff190000 {
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compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff190000 0x0 0x100>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart3: serial@ff1b0000 {
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compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff1b0000 0x0 0x100>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart4: serial@ff1c0000 {
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compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff1c0000 0x0 0x100>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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|
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thermal-zones {
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cpu {
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polling-delay-passive = <100>; /* milliseconds */
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polling-delay = <5000>; /* milliseconds */
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|
|
thermal-sensors = <&tsadc 0>;
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|
|
|
trips {
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|
cpu_alert0: cpu_alert0 {
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temperature = <75000>; /* millicelsius */
|
|
hysteresis = <2000>; /* millicelsius */
|
|
type = "passive";
|
|
};
|
|
cpu_alert1: cpu_alert1 {
|
|
temperature = <80000>; /* millicelsius */
|
|
hysteresis = <2000>; /* millicelsius */
|
|
type = "passive";
|
|
};
|
|
cpu_crit: cpu_crit {
|
|
temperature = <95000>; /* millicelsius */
|
|
hysteresis = <2000>; /* millicelsius */
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu_alert0>;
|
|
cooling-device =
|
|
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
map1 {
|
|
trip = <&cpu_alert1>;
|
|
cooling-device =
|
|
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu {
|
|
polling-delay-passive = <100>; /* milliseconds */
|
|
polling-delay = <5000>; /* milliseconds */
|
|
|
|
thermal-sensors = <&tsadc 1>;
|
|
|
|
trips {
|
|
gpu_alert0: gpu_alert0 {
|
|
temperature = <80000>; /* millicelsius */
|
|
hysteresis = <2000>; /* millicelsius */
|
|
type = "passive";
|
|
};
|
|
gpu_crit: gpu_crit {
|
|
temperature = <115000>; /* millicelsius */
|
|
hysteresis = <2000>; /* millicelsius */
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&gpu_alert0>;
|
|
cooling-device =
|
|
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tsadc: tsadc@ff280000 {
|
|
compatible = "rockchip,rk3368-tsadc";
|
|
reg = <0x0 0xff280000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
|
|
clock-names = "tsadc", "apb_pclk";
|
|
resets = <&cru SRST_TSADC>;
|
|
reset-names = "tsadc-apb";
|
|
pinctrl-names = "init", "default", "sleep";
|
|
pinctrl-0 = <&otp_gpio>;
|
|
pinctrl-1 = <&otp_out>;
|
|
pinctrl-2 = <&otp_gpio>;
|
|
#thermal-sensor-cells = <1>;
|
|
rockchip,hw-tshut-temp = <95000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac: ethernet@ff290000 {
|
|
compatible = "rockchip,rk3368-gmac";
|
|
reg = <0x0 0xff290000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
rockchip,grf = <&grf>;
|
|
clocks = <&cru SCLK_MAC>,
|
|
<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
|
|
<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
|
|
<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
|
|
clock-names = "stmmaceth",
|
|
"mac_clk_rx", "mac_clk_tx",
|
|
"clk_mac_ref", "clk_mac_refout",
|
|
"aclk_mac", "pclk_mac";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_host0_ehci: usb@ff500000 {
|
|
compatible = "generic-ehci";
|
|
reg = <0x0 0xff500000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_HOST0>;
|
|
clock-names = "usbhost";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_otg: usb@ff580000 {
|
|
compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
|
|
"snps,dwc2";
|
|
reg = <0x0 0xff580000 0x0 0x40000>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_OTG0>;
|
|
clock-names = "otg";
|
|
dr_mode = "otg";
|
|
g-np-tx-fifo-size = <16>;
|
|
g-rx-fifo-size = <275>;
|
|
g-tx-fifo-size = <256 128 128 64 64 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@ff650000 {
|
|
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
|
|
reg = <0x0 0xff650000 0x0 0x1000>;
|
|
clocks = <&cru PCLK_I2C0>;
|
|
clock-names = "i2c";
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@ff660000 {
|
|
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
|
|
reg = <0x0 0xff660000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "i2c";
|
|
clocks = <&cru PCLK_I2C1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@ff680000 {
|
|
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff680000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm0_pin>;
|
|
clocks = <&cru PCLK_PWM1>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@ff680010 {
|
|
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff680010 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm1_pin>;
|
|
clocks = <&cru PCLK_PWM1>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@ff680020 {
|
|
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff680020 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&cru PCLK_PWM1>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@ff680030 {
|
|
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff680030 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm3_pin>;
|
|
clocks = <&cru PCLK_PWM1>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@ff690000 {
|
|
compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff690000 0x0 0x100>;
|
|
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart2_xfer>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mbox: mbox@ff6b0000 {
|
|
compatible = "rockchip,rk3368-mailbox";
|
|
reg = <0x0 0xff6b0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_MAILBOX>;
|
|
clock-names = "pclk_mailbox";
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pmugrf: syscon@ff738000 {
|
|
compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
|
|
reg = <0x0 0xff738000 0x0 0x1000>;
|
|
|
|
pmu_io_domains: io-domains {
|
|
compatible = "rockchip,rk3368-pmu-io-voltage-domain";
|
|
status = "disabled";
|
|
};
|
|
|
|
reboot-mode {
|
|
compatible = "syscon-reboot-mode";
|
|
offset = <0x200>;
|
|
mode-normal = <BOOT_NORMAL>;
|
|
mode-recovery = <BOOT_RECOVERY>;
|
|
mode-bootloader = <BOOT_FASTBOOT>;
|
|
mode-loader = <BOOT_BL_DOWNLOAD>;
|
|
};
|
|
};
|
|
|
|
cru: clock-controller@ff760000 {
|
|
compatible = "rockchip,rk3368-cru";
|
|
reg = <0x0 0xff760000 0x0 0x1000>;
|
|
rockchip,grf = <&grf>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
grf: syscon@ff770000 {
|
|
compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
|
|
reg = <0x0 0xff770000 0x0 0x1000>;
|
|
|
|
io_domains: io-domains {
|
|
compatible = "rockchip,rk3368-io-voltage-domain";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
wdt: watchdog@ff800000 {
|
|
compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
|
|
reg = <0x0 0xff800000 0x0 0x100>;
|
|
clocks = <&cru PCLK_WDT>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@ff810000 {
|
|
compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
|
|
reg = <0x0 0xff810000 0x0 0x20>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
spdif: spdif@ff880000 {
|
|
compatible = "rockchip,rk3368-spdif";
|
|
reg = <0x0 0xff880000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
|
|
clock-names = "mclk", "hclk";
|
|
dmas = <&dmac_bus 3>;
|
|
dma-names = "tx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spdif_tx>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s_2ch: i2s-2ch@ff890000 {
|
|
compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x0 0xff890000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "i2s_clk", "i2s_hclk";
|
|
clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
|
|
dmas = <&dmac_bus 6>, <&dmac_bus 7>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s_8ch: i2s-8ch@ff898000 {
|
|
compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x0 0xff898000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "i2s_clk", "i2s_hclk";
|
|
clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
|
|
dmas = <&dmac_bus 0>, <&dmac_bus 1>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s_8ch_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iep_mmu: iommu@ff900800 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff900800 0x0 0x100>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-names = "iep_mmu";
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
isp_mmu: iommu@ff914000 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff914000 0x0 0x100>,
|
|
<0x0 0xff915000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "isp_mmu";
|
|
#iommu-cells = <0>;
|
|
rockchip,disable-mmu-reset;
|
|
status = "disabled";
|
|
};
|
|
|
|
vop_mmu: iommu@ff930300 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff930300 0x0 0x100>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "vop_mmu";
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hevc_mmu: iommu@ff9a0440 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff9a0440 0x0 0x40>,
|
|
<0x0 0xff9a0480 0x0 0x40>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hevc_mmu";
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vpu_mmu: iommu@ff9a0800 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff9a0800 0x0 0x100>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "vepu_mmu", "vdpu_mmu";
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@ffb71000 {
|
|
compatible = "arm,gic-400";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
|
|
reg = <0x0 0xffb71000 0x0 0x1000>,
|
|
<0x0 0xffb72000 0x0 0x2000>,
|
|
<0x0 0xffb74000 0x0 0x2000>,
|
|
<0x0 0xffb76000 0x0 0x2000>;
|
|
interrupts = <GIC_PPI 9
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rk3368-pinctrl";
|
|
rockchip,grf = <&grf>;
|
|
rockchip,pmu = <&pmugrf>;
|
|
#address-cells = <0x2>;
|
|
#size-cells = <0x2>;
|
|
ranges;
|
|
|
|
gpio0: gpio0@ff750000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff750000 0x0 0x100>;
|
|
clocks = <&cru PCLK_GPIO0>;
|
|
interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
gpio1: gpio1@ff780000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff780000 0x0 0x100>;
|
|
clocks = <&cru PCLK_GPIO1>;
|
|
interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
gpio2: gpio2@ff790000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff790000 0x0 0x100>;
|
|
clocks = <&cru PCLK_GPIO2>;
|
|
interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
gpio3: gpio3@ff7a0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff7a0000 0x0 0x100>;
|
|
clocks = <&cru PCLK_GPIO3>;
|
|
interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
pcfg_pull_up: pcfg-pull-up {
|
|
bias-pull-up;
|
|
};
|
|
|
|
pcfg_pull_down: pcfg-pull-down {
|
|
bias-pull-down;
|
|
};
|
|
|
|
pcfg_pull_none: pcfg-pull-none {
|
|
bias-disable;
|
|
};
|
|
|
|
pcfg_pull_none_12ma: pcfg-pull-none-12ma {
|
|
bias-disable;
|
|
drive-strength = <12>;
|
|
};
|
|
|
|
emmc {
|
|
emmc_clk: emmc-clk {
|
|
rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
emmc_cmd: emmc-cmd {
|
|
rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_pwr: emmc-pwr {
|
|
rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_bus1: emmc-bus1 {
|
|
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_bus4: emmc-bus4 {
|
|
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
|
|
<1 19 RK_FUNC_2 &pcfg_pull_up>,
|
|
<1 20 RK_FUNC_2 &pcfg_pull_up>,
|
|
<1 21 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_bus8: emmc-bus8 {
|
|
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
|
|
<1 19 RK_FUNC_2 &pcfg_pull_up>,
|
|
<1 20 RK_FUNC_2 &pcfg_pull_up>,
|
|
<1 21 RK_FUNC_2 &pcfg_pull_up>,
|
|
<1 22 RK_FUNC_2 &pcfg_pull_up>,
|
|
<1 23 RK_FUNC_2 &pcfg_pull_up>,
|
|
<1 24 RK_FUNC_2 &pcfg_pull_up>,
|
|
<1 25 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
gmac {
|
|
rgmii_pins: rgmii-pins {
|
|
rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 24 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 19 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
|
|
<3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
|
|
<3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
|
|
<3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
|
|
<3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
|
|
<3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
|
|
<3 15 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 16 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 17 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 18 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 25 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 20 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
rmii_pins: rmii-pins {
|
|
rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 24 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 19 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
|
|
<3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
|
|
<3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
|
|
<3 15 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 16 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 20 RK_FUNC_1 &pcfg_pull_none>,
|
|
<3 21 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c0 {
|
|
i2c0_xfer: i2c0-xfer {
|
|
rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 7 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
i2c1_xfer: i2c1-xfer {
|
|
rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 22 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
i2c2_xfer: i2c2-xfer {
|
|
rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
|
|
<3 31 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c3 {
|
|
i2c3_xfer: i2c3-xfer {
|
|
rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
|
|
<1 17 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c4 {
|
|
i2c4_xfer: i2c4-xfer {
|
|
rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
|
|
<3 25 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c5 {
|
|
i2c5_xfer: i2c5-xfer {
|
|
rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
|
|
<3 27 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s {
|
|
i2s_8ch_bus: i2s-8ch-bus {
|
|
rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 13 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 14 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 15 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 16 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 17 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 18 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 19 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 20 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0_pin: pwm0-pin {
|
|
rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm1 {
|
|
pwm1_pin: pwm1-pin {
|
|
rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm3 {
|
|
pwm3_pin: pwm3-pin {
|
|
rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sdio0 {
|
|
sdio0_bus1: sdio0-bus1 {
|
|
rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_bus4: sdio0-bus4 {
|
|
rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
|
|
<2 29 RK_FUNC_1 &pcfg_pull_up>,
|
|
<2 30 RK_FUNC_1 &pcfg_pull_up>,
|
|
<2 31 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_cmd: sdio0-cmd {
|
|
rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_clk: sdio0-clk {
|
|
rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sdio0_cd: sdio0-cd {
|
|
rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_wp: sdio0-wp {
|
|
rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_pwr: sdio0-pwr {
|
|
rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_bkpwr: sdio0-bkpwr {
|
|
rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_int: sdio0-int {
|
|
rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
sdmmc {
|
|
sdmmc_clk: sdmmc-clk {
|
|
rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sdmmc_cmd: sdmmc-cmd {
|
|
rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_cd: sdmmc-cd {
|
|
rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_bus1: sdmmc-bus1 {
|
|
rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_bus4: sdmmc-bus4 {
|
|
rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
|
|
<2 6 RK_FUNC_1 &pcfg_pull_up>,
|
|
<2 7 RK_FUNC_1 &pcfg_pull_up>,
|
|
<2 8 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spdif {
|
|
spdif_tx: spdif-tx {
|
|
rockchip,pins = <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
spi0_clk: spi0-clk {
|
|
rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi0_cs0: spi0-cs0 {
|
|
rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
|
|
};
|
|
spi0_cs1: spi0-cs1 {
|
|
rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
|
|
};
|
|
spi0_tx: spi0-tx {
|
|
rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
|
|
};
|
|
spi0_rx: spi0-rx {
|
|
rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
spi1_clk: spi1-clk {
|
|
rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi1_cs0: spi1-cs0 {
|
|
rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi1_cs1: spi1-cs1 {
|
|
rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi1_rx: spi1-rx {
|
|
rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi1_tx: spi1-tx {
|
|
rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi2 {
|
|
spi2_clk: spi2-clk {
|
|
rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi2_cs0: spi2-cs0 {
|
|
rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi2_rx: spi2-rx {
|
|
rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi2_tx: spi2-tx {
|
|
rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
tsadc {
|
|
otp_gpio: otp-gpio {
|
|
rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
otp_out: otp-out {
|
|
rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
|
|
<2 25 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
|
|
<0 21 RK_FUNC_3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_cts: uart1-cts {
|
|
rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_rts: uart1-rts {
|
|
rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
uart2_xfer: uart2-xfer {
|
|
rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
|
|
<2 5 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
/* no rts / cts for uart2 */
|
|
};
|
|
|
|
uart3 {
|
|
uart3_xfer: uart3-xfer {
|
|
rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
|
|
<3 30 RK_FUNC_3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3_cts: uart3-cts {
|
|
rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3_rts: uart3-rts {
|
|
rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart4 {
|
|
uart4_xfer: uart4-xfer {
|
|
rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
|
|
<0 26 RK_FUNC_3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart4_cts: uart4-cts {
|
|
rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart4_rts: uart4-rts {
|
|
rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
};
|