Jon Hunter 2956994168 clk: tegra: Add the APB2APE audio clock on Tegra210 ... The APB2APE clock for the audio subsystem is required for powering up the audio power domain and accessing the various modules in this subsystem on Tegra210 devices. Add this clock for Tegra210. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>		2016-02-02 15:49:29 +01:00
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arm
clk
clock	clk: tegra: Add the APB2APE audio clock on Tegra210	2016-02-02 15:49:29 +01:00
dma
gpio
i2c
iio
input
interrupt-controller
leds	dt-bindings: fixes some incorrect header guards	2015-12-08 15:06:54 +01:00
media
memory
mfd	dt-bindings: fixes some incorrect header guards	2015-12-08 15:06:54 +01:00
net
phy
pinctrl	Add minimal device tree support for dra62x also known j5eco. It is	2015-12-31 16:25:22 +01:00
power	ARM: bcm2835: add rpi power domain driver	2015-12-21 20:00:41 -08:00
pwm
regulator
reset	ARM: SoC driver updates for v4.5	2016-01-20 18:42:30 -08:00
soc
sound
spmi
thermal