mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 09:40:57 +07:00
0b8439d374
- Move IRQ register address computation inside macros (Kishon Vijay Abraham I) - Separate legacy IRQ and MSI configuration (Kishon Vijay Abraham I) - Use hwirq, not virq, to get MSI IRQ number offset (Kishon Vijay Abraham I) - Squash ks_pcie_handle_msi_irq() into ks_pcie_msi_irq_handler() (Kishon Vijay Abraham I) - Add dwc support for platforms with custom MSI controllers (Kishon Vijay Abraham I) - Add keystone-specific MSI controller (Kishon Vijay Abraham I) - Remove dwc host_ops previously used for keystone-specific MSI (Kishon Vijay Abraham I) - Skip dwc default MSI init if platform has custom MSI controller (Kishon Vijay Abraham I) - Implement .start_link() and .stop_link() for keystone endpoint support (Kishon Vijay Abraham I) - Add keystone "reg-names" DT binding (Kishon Vijay Abraham I) - Squash ks_pcie_dw_host_init() into ks_pcie_add_pcie_port() (Kishon Vijay Abraham I) - Get keystone register resources from DT by name, not index (Kishon Vijay Abraham I) - Get DT resources in .probe() to prepare for endpoint support (Kishon Vijay Abraham I) - Add "ti,syscon-pcie-mode" DT property for PCIe mode configuration (Kishon Vijay Abraham I) - Explicitly set keystone to host mode (Kishon Vijay Abraham I) - Document DT "atu" reg-names requirement for DesignWare core >= 4.80 (Kishon Vijay Abraham I) - Enable dwc iATU unroll for endpoint mode as well as host mode (Kishon Vijay Abraham I) - Add dwc "version" to identify core >= 4.80 for ATU programming (Kishon Vijay Abraham I) - Don't build ARM32-specific keystone code on ARM64 (Kishon Vijay Abraham I) - Add DT binding for keystone PCIe RC in AM654 SoC (Kishon Vijay Abraham I) - Add keystone support for AM654 SoC PCIe RC (Kishon Vijay Abraham I) - Reset keystone PHYs before enabling them (Kishon Vijay Abraham I) - Make of_pci_get_max_link_speed() available to endpoint drivers as well as host drivers (Kishon Vijay Abraham I) - Add keystone support for DT "max-link-speed" property (Kishon Vijay Abraham I) - Add endpoint library support for BAR buffer alignment (Kishon Vijay Abraham I) - Make all dw_pcie_ep_ops structs const (Kishon Vijay Abraham I) - Fix fencepost error in dw_pcie_ep_find_capability() (Kishon Vijay Abraham I) - Add dwc hooks for dbi/dbi2 that share the same address space (Kishon Vijay Abraham I) - Add keystone support for TI AM654x in endpoint mode (Kishon Vijay Abraham I) - Configure designware endpoints to advertise smallest resizable BAR (1MB) (Kishon Vijay Abraham I) - Align designware endpoint ATU windows for raising MSIs (Kishon Vijay Abraham I) - Add endpoint test support for TI AM654x (Kishon Vijay Abraham I) - Fix endpoint test test_reg_bar issue (Kishon Vijay Abraham I) * remotes/lorenzo/pci/keystone: misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test misc: pci_endpoint_test: Add support to test PCI EP in AM654x PCI: designware-ep: Use aligned ATU window for raising MSI interrupts PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest size PCI: keystone: Add support for PCIe EP in AM654x Platforms dt-bindings: PCI: Add PCI EP DT binding documentation for AM654 PCI: dwc: Add callbacks for accessing dbi2 address space PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offset PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops PCI: endpoint: Add support to specify alignment for buffers allocated to BARs PCI: keystone: Add support to set the max link speed from DT PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers PCI: keystone: Invoke phy_reset() API before enabling PHY PCI: keystone: Add support for PCIe RC in AM654x Platforms dt-bindings: PCI: Add PCI RC DT binding documentation for AM654 PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 PCI: dwc: Fix ATU identification for designware version >= 4.80 PCI: dwc: Enable iATU unroll for endpoint too dt-bindings: PCI: Document "atu" reg-names PCI: keystone: Explicitly set the PCIe mode dt-bindings: PCI: Add dt-binding to configure PCIe mode PCI: keystone: Move resources initialization to prepare for EP support PCI: keystone: Use platform_get_resource_byname() to get memory resources PCI: keystone: Perform host initialization in a single function dt-bindings: PCI: keystone: Add "reg-names" binding information PCI: keystone: Cleanup error_irq configuration PCI: keystone: Add start_link()/stop_link() dw_pcie_ops PCI: dwc: Remove default MSI initialization for platform specific MSI chips PCI: dwc: Remove Keystone specific dw_pcie_host_ops PCI: keystone: Use Keystone specific msi_irq_chip PCI: dwc: Add support to use non default msi_irq_chip PCI: keystone: Cleanup ks_pcie_msi_irq_handler() PCI: keystone: Use hwirq to get the MSI IRQ number offset PCI: keystone: Add separate functions for configuring MSI and legacy interrupt PCI: keystone: Cleanup interrupt related macros # Conflicts: # drivers/pci/controller/dwc/pcie-designware.h
690 lines
17 KiB
C
690 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Synopsys DesignWare PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*/
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/pci_regs.h>
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#include <linux/platform_device.h>
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#include "../../pci.h"
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#include "pcie-designware.h"
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static struct pci_ops dw_pcie_ops;
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static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
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u32 *val)
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{
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struct dw_pcie *pci;
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if (pp->ops->rd_own_conf)
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return pp->ops->rd_own_conf(pp, where, size, val);
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pci = to_dw_pcie_from_pp(pp);
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return dw_pcie_read(pci->dbi_base + where, size, val);
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}
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static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
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u32 val)
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{
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struct dw_pcie *pci;
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if (pp->ops->wr_own_conf)
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return pp->ops->wr_own_conf(pp, where, size, val);
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pci = to_dw_pcie_from_pp(pp);
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return dw_pcie_write(pci->dbi_base + where, size, val);
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}
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static void dw_msi_ack_irq(struct irq_data *d)
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{
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irq_chip_ack_parent(d);
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}
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static void dw_msi_mask_irq(struct irq_data *d)
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{
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pci_msi_mask_irq(d);
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irq_chip_mask_parent(d);
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}
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static void dw_msi_unmask_irq(struct irq_data *d)
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{
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pci_msi_unmask_irq(d);
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irq_chip_unmask_parent(d);
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}
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static struct irq_chip dw_pcie_msi_irq_chip = {
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.name = "PCI-MSI",
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.irq_ack = dw_msi_ack_irq,
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.irq_mask = dw_msi_mask_irq,
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.irq_unmask = dw_msi_unmask_irq,
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};
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static struct msi_domain_info dw_pcie_msi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
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.chip = &dw_pcie_msi_irq_chip,
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};
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/* MSI int handler */
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irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
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{
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int i, pos, irq;
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u32 val, num_ctrls;
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irqreturn_t ret = IRQ_NONE;
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num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
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for (i = 0; i < num_ctrls; i++) {
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS +
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(i * MSI_REG_CTRL_BLOCK_SIZE),
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4, &val);
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if (!val)
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continue;
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ret = IRQ_HANDLED;
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pos = 0;
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while ((pos = find_next_bit((unsigned long *) &val,
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MAX_MSI_IRQS_PER_CTRL,
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pos)) != MAX_MSI_IRQS_PER_CTRL) {
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irq = irq_find_mapping(pp->irq_domain,
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(i * MAX_MSI_IRQS_PER_CTRL) +
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pos);
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generic_handle_irq(irq);
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pos++;
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}
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}
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return ret;
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}
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/* Chained MSI interrupt service routine */
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static void dw_chained_msi_isr(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct pcie_port *pp;
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chained_irq_enter(chip, desc);
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pp = irq_desc_get_handler_data(desc);
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dw_handle_msi_irq(pp);
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chained_irq_exit(chip, desc);
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}
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static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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u64 msi_target;
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msi_target = (u64)pp->msi_data;
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msg->address_lo = lower_32_bits(msi_target);
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msg->address_hi = upper_32_bits(msi_target);
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msg->data = d->hwirq;
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dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
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(int)d->hwirq, msg->address_hi, msg->address_lo);
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}
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static int dw_pci_msi_set_affinity(struct irq_data *d,
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const struct cpumask *mask, bool force)
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{
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return -EINVAL;
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}
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static void dw_pci_bottom_mask(struct irq_data *d)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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unsigned int res, bit, ctrl;
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unsigned long flags;
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raw_spin_lock_irqsave(&pp->lock, flags);
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ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
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res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
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bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
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pp->irq_mask[ctrl] |= BIT(bit);
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
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pp->irq_mask[ctrl]);
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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}
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static void dw_pci_bottom_unmask(struct irq_data *d)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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unsigned int res, bit, ctrl;
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unsigned long flags;
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raw_spin_lock_irqsave(&pp->lock, flags);
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ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
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res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
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bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
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pp->irq_mask[ctrl] &= ~BIT(bit);
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
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pp->irq_mask[ctrl]);
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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}
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static void dw_pci_bottom_ack(struct irq_data *d)
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{
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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unsigned int res, bit, ctrl;
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ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
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res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
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bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit));
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}
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static struct irq_chip dw_pci_msi_bottom_irq_chip = {
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.name = "DWPCI-MSI",
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.irq_ack = dw_pci_bottom_ack,
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.irq_compose_msi_msg = dw_pci_setup_msi_msg,
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.irq_set_affinity = dw_pci_msi_set_affinity,
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.irq_mask = dw_pci_bottom_mask,
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.irq_unmask = dw_pci_bottom_unmask,
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};
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static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs,
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void *args)
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{
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struct pcie_port *pp = domain->host_data;
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unsigned long flags;
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u32 i;
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int bit;
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raw_spin_lock_irqsave(&pp->lock, flags);
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bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
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order_base_2(nr_irqs));
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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if (bit < 0)
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return -ENOSPC;
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_info(domain, virq + i, bit + i,
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pp->msi_irq_chip,
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pp, handle_edge_irq,
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NULL, NULL);
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return 0;
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}
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static void dw_pcie_irq_domain_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct pcie_port *pp = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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raw_spin_lock_irqsave(&pp->lock, flags);
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bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
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order_base_2(nr_irqs));
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raw_spin_unlock_irqrestore(&pp->lock, flags);
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}
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static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
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.alloc = dw_pcie_irq_domain_alloc,
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.free = dw_pcie_irq_domain_free,
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};
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int dw_pcie_allocate_domains(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
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pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
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&dw_pcie_msi_domain_ops, pp);
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if (!pp->irq_domain) {
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dev_err(pci->dev, "Failed to create IRQ domain\n");
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return -ENOMEM;
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}
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pp->msi_domain = pci_msi_create_irq_domain(fwnode,
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&dw_pcie_msi_domain_info,
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pp->irq_domain);
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if (!pp->msi_domain) {
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dev_err(pci->dev, "Failed to create MSI domain\n");
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irq_domain_remove(pp->irq_domain);
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return -ENOMEM;
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}
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return 0;
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}
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void dw_pcie_free_msi(struct pcie_port *pp)
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{
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if (pp->msi_irq) {
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irq_set_chained_handler(pp->msi_irq, NULL);
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irq_set_handler_data(pp->msi_irq, NULL);
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}
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irq_domain_remove(pp->msi_domain);
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irq_domain_remove(pp->irq_domain);
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if (pp->msi_page)
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__free_page(pp->msi_page);
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}
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void dw_pcie_msi_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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u64 msi_target;
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pp->msi_page = alloc_page(GFP_KERNEL);
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pp->msi_data = dma_map_page(dev, pp->msi_page, 0, PAGE_SIZE,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(dev, pp->msi_data)) {
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dev_err(dev, "Failed to map MSI data\n");
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__free_page(pp->msi_page);
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pp->msi_page = NULL;
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return;
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}
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msi_target = (u64)pp->msi_data;
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/* Program the msi_data */
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dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
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lower_32_bits(msi_target));
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dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
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upper_32_bits(msi_target));
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}
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int dw_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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struct device_node *np = dev->of_node;
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struct platform_device *pdev = to_platform_device(dev);
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struct resource_entry *win, *tmp;
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struct pci_bus *child;
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struct pci_host_bridge *bridge;
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struct resource *cfg_res;
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int ret;
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raw_spin_lock_init(&pci->pp.lock);
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cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
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if (cfg_res) {
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pp->cfg0_size = resource_size(cfg_res) >> 1;
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pp->cfg1_size = resource_size(cfg_res) >> 1;
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pp->cfg0_base = cfg_res->start;
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pp->cfg1_base = cfg_res->start + pp->cfg0_size;
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} else if (!pp->va_cfg0_base) {
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dev_err(dev, "Missing *config* reg space\n");
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}
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bridge = devm_pci_alloc_host_bridge(dev, 0);
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if (!bridge)
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return -ENOMEM;
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ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
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&bridge->windows, &pp->io_base);
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if (ret)
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return ret;
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ret = devm_request_pci_bus_resources(dev, &bridge->windows);
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if (ret)
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return ret;
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/* Get the I/O and memory ranges from DT */
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resource_list_for_each_entry_safe(win, tmp, &bridge->windows) {
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switch (resource_type(win->res)) {
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case IORESOURCE_IO:
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ret = devm_pci_remap_iospace(dev, win->res,
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pp->io_base);
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if (ret) {
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dev_warn(dev, "Error %d: failed to map resource %pR\n",
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ret, win->res);
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resource_list_destroy_entry(win);
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} else {
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pp->io = win->res;
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pp->io->name = "I/O";
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pp->io_size = resource_size(pp->io);
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pp->io_bus_addr = pp->io->start - win->offset;
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}
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break;
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case IORESOURCE_MEM:
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pp->mem = win->res;
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pp->mem->name = "MEM";
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pp->mem_size = resource_size(pp->mem);
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pp->mem_bus_addr = pp->mem->start - win->offset;
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break;
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case 0:
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pp->cfg = win->res;
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pp->cfg0_size = resource_size(pp->cfg) >> 1;
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pp->cfg1_size = resource_size(pp->cfg) >> 1;
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pp->cfg0_base = pp->cfg->start;
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pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
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break;
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case IORESOURCE_BUS:
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pp->busn = win->res;
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break;
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}
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}
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if (!pci->dbi_base) {
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pci->dbi_base = devm_pci_remap_cfgspace(dev,
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pp->cfg->start,
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resource_size(pp->cfg));
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if (!pci->dbi_base) {
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dev_err(dev, "Error with ioremap\n");
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
pp->mem_base = pp->mem->start;
|
|
|
|
if (!pp->va_cfg0_base) {
|
|
pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
|
|
pp->cfg0_base, pp->cfg0_size);
|
|
if (!pp->va_cfg0_base) {
|
|
dev_err(dev, "Error with ioremap in function\n");
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
if (!pp->va_cfg1_base) {
|
|
pp->va_cfg1_base = devm_pci_remap_cfgspace(dev,
|
|
pp->cfg1_base,
|
|
pp->cfg1_size);
|
|
if (!pp->va_cfg1_base) {
|
|
dev_err(dev, "Error with ioremap\n");
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
|
|
if (ret)
|
|
pci->num_viewport = 2;
|
|
|
|
if (pci_msi_enabled()) {
|
|
/*
|
|
* If a specific SoC driver needs to change the
|
|
* default number of vectors, it needs to implement
|
|
* the set_num_vectors callback.
|
|
*/
|
|
if (!pp->ops->set_num_vectors) {
|
|
pp->num_vectors = MSI_DEF_NUM_VECTORS;
|
|
} else {
|
|
pp->ops->set_num_vectors(pp);
|
|
|
|
if (pp->num_vectors > MAX_MSI_IRQS ||
|
|
pp->num_vectors == 0) {
|
|
dev_err(dev,
|
|
"Invalid number of vectors\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
if (!pp->ops->msi_host_init) {
|
|
pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
|
|
|
|
ret = dw_pcie_allocate_domains(pp);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (pp->msi_irq)
|
|
irq_set_chained_handler_and_data(pp->msi_irq,
|
|
dw_chained_msi_isr,
|
|
pp);
|
|
} else {
|
|
ret = pp->ops->msi_host_init(pp);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (pp->ops->host_init) {
|
|
ret = pp->ops->host_init(pp);
|
|
if (ret)
|
|
goto err_free_msi;
|
|
}
|
|
|
|
pp->root_bus_nr = pp->busn->start;
|
|
|
|
bridge->dev.parent = dev;
|
|
bridge->sysdata = pp;
|
|
bridge->busnr = pp->root_bus_nr;
|
|
bridge->ops = &dw_pcie_ops;
|
|
bridge->map_irq = of_irq_parse_and_map_pci;
|
|
bridge->swizzle_irq = pci_common_swizzle;
|
|
|
|
ret = pci_scan_root_bus_bridge(bridge);
|
|
if (ret)
|
|
goto err_free_msi;
|
|
|
|
pp->root_bus = bridge->bus;
|
|
|
|
if (pp->ops->scan_bus)
|
|
pp->ops->scan_bus(pp);
|
|
|
|
pci_bus_size_bridges(pp->root_bus);
|
|
pci_bus_assign_resources(pp->root_bus);
|
|
|
|
list_for_each_entry(child, &pp->root_bus->children, node)
|
|
pcie_bus_configure_settings(child);
|
|
|
|
pci_bus_add_devices(pp->root_bus);
|
|
return 0;
|
|
|
|
err_free_msi:
|
|
if (pci_msi_enabled() && !pp->ops->msi_host_init)
|
|
dw_pcie_free_msi(pp);
|
|
return ret;
|
|
}
|
|
|
|
static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus,
|
|
u32 devfn, int where, int size, u32 *val,
|
|
bool write)
|
|
{
|
|
int ret, type;
|
|
u32 busdev, cfg_size;
|
|
u64 cpu_addr;
|
|
void __iomem *va_cfg_base;
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
|
|
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
|
|
PCIE_ATU_FUNC(PCI_FUNC(devfn));
|
|
|
|
if (bus->parent->number == pp->root_bus_nr) {
|
|
type = PCIE_ATU_TYPE_CFG0;
|
|
cpu_addr = pp->cfg0_base;
|
|
cfg_size = pp->cfg0_size;
|
|
va_cfg_base = pp->va_cfg0_base;
|
|
} else {
|
|
type = PCIE_ATU_TYPE_CFG1;
|
|
cpu_addr = pp->cfg1_base;
|
|
cfg_size = pp->cfg1_size;
|
|
va_cfg_base = pp->va_cfg1_base;
|
|
}
|
|
|
|
dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
|
|
type, cpu_addr,
|
|
busdev, cfg_size);
|
|
if (write)
|
|
ret = dw_pcie_write(va_cfg_base + where, size, *val);
|
|
else
|
|
ret = dw_pcie_read(va_cfg_base + where, size, val);
|
|
|
|
if (pci->num_viewport <= 2)
|
|
dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
|
|
PCIE_ATU_TYPE_IO, pp->io_base,
|
|
pp->io_bus_addr, pp->io_size);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
|
|
u32 devfn, int where, int size, u32 *val)
|
|
{
|
|
if (pp->ops->rd_other_conf)
|
|
return pp->ops->rd_other_conf(pp, bus, devfn, where,
|
|
size, val);
|
|
|
|
return dw_pcie_access_other_conf(pp, bus, devfn, where, size, val,
|
|
false);
|
|
}
|
|
|
|
static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
|
|
u32 devfn, int where, int size, u32 val)
|
|
{
|
|
if (pp->ops->wr_other_conf)
|
|
return pp->ops->wr_other_conf(pp, bus, devfn, where,
|
|
size, val);
|
|
|
|
return dw_pcie_access_other_conf(pp, bus, devfn, where, size, &val,
|
|
true);
|
|
}
|
|
|
|
static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
|
|
int dev)
|
|
{
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
|
|
/* If there is no link, then there is no device */
|
|
if (bus->number != pp->root_bus_nr) {
|
|
if (!dw_pcie_link_up(pci))
|
|
return 0;
|
|
}
|
|
|
|
/* Access only one slot on each root port */
|
|
if (bus->number == pp->root_bus_nr && dev > 0)
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
|
|
int size, u32 *val)
|
|
{
|
|
struct pcie_port *pp = bus->sysdata;
|
|
|
|
if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
|
|
*val = 0xffffffff;
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
}
|
|
|
|
if (bus->number == pp->root_bus_nr)
|
|
return dw_pcie_rd_own_conf(pp, where, size, val);
|
|
|
|
return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
|
|
}
|
|
|
|
static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
|
|
int where, int size, u32 val)
|
|
{
|
|
struct pcie_port *pp = bus->sysdata;
|
|
|
|
if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
if (bus->number == pp->root_bus_nr)
|
|
return dw_pcie_wr_own_conf(pp, where, size, val);
|
|
|
|
return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
|
|
}
|
|
|
|
static struct pci_ops dw_pcie_ops = {
|
|
.read = dw_pcie_rd_conf,
|
|
.write = dw_pcie_wr_conf,
|
|
};
|
|
|
|
void dw_pcie_setup_rc(struct pcie_port *pp)
|
|
{
|
|
u32 val, ctrl, num_ctrls;
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
|
|
dw_pcie_setup(pci);
|
|
|
|
if (!pp->ops->msi_host_init) {
|
|
num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
|
|
|
|
/* Initialize IRQ Status array */
|
|
for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
|
|
pp->irq_mask[ctrl] = ~0;
|
|
dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK +
|
|
(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
|
|
4, pp->irq_mask[ctrl]);
|
|
dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
|
|
(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
|
|
4, ~0);
|
|
}
|
|
}
|
|
|
|
/* Setup RC BARs */
|
|
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
|
|
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
|
|
|
|
/* Setup interrupt pins */
|
|
dw_pcie_dbi_ro_wr_en(pci);
|
|
val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
|
|
val &= 0xffff00ff;
|
|
val |= 0x00000100;
|
|
dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
|
|
dw_pcie_dbi_ro_wr_dis(pci);
|
|
|
|
/* Setup bus numbers */
|
|
val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
|
|
val &= 0xff000000;
|
|
val |= 0x00ff0100;
|
|
dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
|
|
|
|
/* Setup command register */
|
|
val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
|
|
val &= 0xffff0000;
|
|
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
|
|
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
|
|
dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
|
|
|
|
/*
|
|
* If the platform provides ->rd_other_conf, it means the platform
|
|
* uses its own address translation component rather than ATU, so
|
|
* we should not program the ATU here.
|
|
*/
|
|
if (!pp->ops->rd_other_conf) {
|
|
dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
|
|
PCIE_ATU_TYPE_MEM, pp->mem_base,
|
|
pp->mem_bus_addr, pp->mem_size);
|
|
if (pci->num_viewport > 2)
|
|
dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,
|
|
PCIE_ATU_TYPE_IO, pp->io_base,
|
|
pp->io_bus_addr, pp->io_size);
|
|
}
|
|
|
|
dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
|
|
|
|
/* Enable write permission for the DBI read-only register */
|
|
dw_pcie_dbi_ro_wr_en(pci);
|
|
/* Program correct class for RC */
|
|
dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
|
|
/* Better disable write permission right after the update */
|
|
dw_pcie_dbi_ro_wr_dis(pci);
|
|
|
|
dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
|
|
val |= PORT_LOGIC_SPEED_CHANGE;
|
|
dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
|
|
}
|