mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 18:05:07 +07:00
bb728d662b
To establish a connection between GPIO controllers and pin multiplexor
controller add gpio-ranges properties to all GPIO controllers found
on iMX50, iMX6Q/D, iMX6DL/S, iMX6SL, iMX6SX, iMX6UL and iMX7D/S
SoCs. The change was done after human parsing of output from
% gawk -n '{ sub(/.*__/, ""); if ($1 ~ "^GPIO") print $1, $2/4}' imxXX-pinfunc.h | sort -n
Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
338 lines
6.9 KiB
Plaintext
338 lines
6.9 KiB
Plaintext
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "imx6q-pinfunc.h"
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#include "imx6qdl.dtsi"
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/ {
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aliases {
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ipu1 = &ipu2;
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spi4 = &ecspi5;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 975000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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cpu@2 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2>;
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};
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};
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soc {
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ocram: sram@00900000 {
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compatible = "mmio-sram";
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reg = <0x00900000 0x40000>;
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clocks = <&clks IMX6QDL_CLK_OCRAM>;
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};
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aips-bus@02000000 { /* AIPS1 */
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spba-bus@02000000 {
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ecspi5: ecspi@02018000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x02018000 0x4000>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6Q_CLK_ECSPI5>,
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<&clks IMX6Q_CLK_ECSPI5>;
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clock-names = "ipg", "per";
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dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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};
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iomuxc: iomuxc@020e0000 {
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compatible = "fsl,imx6q-iomuxc";
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};
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};
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sata: sata@02200000 {
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compatible = "fsl,imx6q-ahci";
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reg = <0x02200000 0x4000>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_SATA>,
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<&clks IMX6QDL_CLK_SATA_REF_100M>,
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<&clks IMX6QDL_CLK_AHB>;
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clock-names = "sata", "sata_ref", "ahb";
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status = "disabled";
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};
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gpu_vg: gpu@02204000 {
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compatible = "vivante,gc";
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reg = <0x02204000 0x4000>;
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interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
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<&clks IMX6QDL_CLK_GPU2D_CORE>;
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clock-names = "bus", "core";
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power-domains = <&gpc 1>;
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};
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ipu2: ipu@02800000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-ipu";
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reg = <0x02800000 0x400000>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_IPU2>,
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<&clks IMX6QDL_CLK_IPU2_DI0>,
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<&clks IMX6QDL_CLK_IPU2_DI1>;
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clock-names = "bus", "di0", "di1";
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resets = <&src 4>;
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ipu2_csi0: port@0 {
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reg = <0>;
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};
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ipu2_csi1: port@1 {
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reg = <1>;
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};
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ipu2_di0: port@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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ipu2_di0_disp0: disp0-endpoint {
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};
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ipu2_di0_hdmi: hdmi-endpoint {
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remote-endpoint = <&hdmi_mux_2>;
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};
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ipu2_di0_mipi: mipi-endpoint {
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remote-endpoint = <&mipi_mux_2>;
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};
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ipu2_di0_lvds0: lvds0-endpoint {
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remote-endpoint = <&lvds0_mux_2>;
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};
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ipu2_di0_lvds1: lvds1-endpoint {
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remote-endpoint = <&lvds1_mux_2>;
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};
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};
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ipu2_di1: port@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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ipu2_di1_hdmi: hdmi-endpoint {
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remote-endpoint = <&hdmi_mux_3>;
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};
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ipu2_di1_mipi: mipi-endpoint {
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remote-endpoint = <&mipi_mux_3>;
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};
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ipu2_di1_lvds0: lvds0-endpoint {
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remote-endpoint = <&lvds0_mux_3>;
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};
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ipu2_di1_lvds1: lvds1-endpoint {
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remote-endpoint = <&lvds1_mux_3>;
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};
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};
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};
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};
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display-subsystem {
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compatible = "fsl,imx-display-subsystem";
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ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
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};
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gpu-subsystem {
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compatible = "fsl,imx-gpu-subsystem";
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cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
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};
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};
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&gpio1 {
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gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
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<&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
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<&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
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<&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
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<&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
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<&iomuxc 22 116 10>;
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};
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&gpio2 {
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gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
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<&iomuxc 31 44 1>;
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};
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&gpio3 {
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gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
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};
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&gpio4 {
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gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
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};
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&gpio5 {
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gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
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<&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
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};
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&gpio6 {
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gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
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<&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
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<&iomuxc 31 86 1>;
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};
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&gpio7 {
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gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
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};
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&hdmi {
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compatible = "fsl,imx6q-hdmi";
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port@2 {
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reg = <2>;
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hdmi_mux_2: endpoint {
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remote-endpoint = <&ipu2_di0_hdmi>;
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};
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};
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port@3 {
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reg = <3>;
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hdmi_mux_3: endpoint {
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remote-endpoint = <&ipu2_di1_hdmi>;
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};
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};
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};
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&ldb {
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clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
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<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
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<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
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clock-names = "di0_pll", "di1_pll",
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"di0_sel", "di1_sel", "di2_sel", "di3_sel",
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"di0", "di1";
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lvds-channel@0 {
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port@2 {
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reg = <2>;
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lvds0_mux_2: endpoint {
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remote-endpoint = <&ipu2_di0_lvds0>;
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};
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};
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port@3 {
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reg = <3>;
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lvds0_mux_3: endpoint {
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remote-endpoint = <&ipu2_di1_lvds0>;
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};
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};
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};
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lvds-channel@1 {
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port@2 {
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reg = <2>;
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lvds1_mux_2: endpoint {
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remote-endpoint = <&ipu2_di0_lvds1>;
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};
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};
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port@3 {
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reg = <3>;
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lvds1_mux_3: endpoint {
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remote-endpoint = <&ipu2_di1_lvds1>;
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};
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};
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};
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};
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&mipi_dsi {
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ports {
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port@2 {
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reg = <2>;
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mipi_mux_2: endpoint {
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remote-endpoint = <&ipu2_di0_mipi>;
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};
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};
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port@3 {
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reg = <3>;
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mipi_mux_3: endpoint {
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remote-endpoint = <&ipu2_di1_mipi>;
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};
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};
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};
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};
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&vpu {
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compatible = "fsl,imx6q-vpu", "cnm,coda960";
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};
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