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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
a7ba70f178
Using a mask to represent bus DMA constraints has a set of limitations. The biggest one being it can only hold a power of two (minus one). The DMA mapping code is already aware of this and treats dev->bus_dma_mask as a limit. This quirk is already used by some architectures although still rare. With the introduction of the Raspberry Pi 4 we've found a new contender for the use of bus DMA limits, as its PCIe bus can only address the lower 3GB of memory (of a total of 4GB). This is impossible to represent with a mask. To make things worse the device-tree code rounds non power of two bus DMA limits to the next power of two, which is unacceptable in this case. In the light of this, rename dev->bus_dma_mask to dev->bus_dma_limit all over the tree and treat it as such. Note that dev->bus_dma_limit should contain the higher accessible DMA address. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
423 lines
11 KiB
C
423 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AMD Memory Encryption Support
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*
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* Copyright (C) 2016 Advanced Micro Devices, Inc.
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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*/
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#define DISABLE_BRANCH_PROFILING
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/dma-direct.h>
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#include <linux/swiotlb.h>
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#include <linux/mem_encrypt.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/dma-mapping.h>
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#include <asm/tlbflush.h>
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#include <asm/fixmap.h>
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#include <asm/setup.h>
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#include <asm/bootparam.h>
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#include <asm/set_memory.h>
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#include <asm/cacheflush.h>
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#include <asm/processor-flags.h>
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#include <asm/msr.h>
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#include <asm/cmdline.h>
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#include "mm_internal.h"
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/*
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* Since SME related variables are set early in the boot process they must
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* reside in the .data section so as not to be zeroed out when the .bss
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* section is later cleared.
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*/
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u64 sme_me_mask __section(.data) = 0;
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EXPORT_SYMBOL(sme_me_mask);
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DEFINE_STATIC_KEY_FALSE(sev_enable_key);
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EXPORT_SYMBOL_GPL(sev_enable_key);
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bool sev_enabled __section(.data);
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/* Buffer used for early in-place encryption by BSP, no locking needed */
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static char sme_early_buffer[PAGE_SIZE] __initdata __aligned(PAGE_SIZE);
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/*
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* This routine does not change the underlying encryption setting of the
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* page(s) that map this memory. It assumes that eventually the memory is
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* meant to be accessed as either encrypted or decrypted but the contents
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* are currently not in the desired state.
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*
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* This routine follows the steps outlined in the AMD64 Architecture
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* Programmer's Manual Volume 2, Section 7.10.8 Encrypt-in-Place.
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*/
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static void __init __sme_early_enc_dec(resource_size_t paddr,
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unsigned long size, bool enc)
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{
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void *src, *dst;
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size_t len;
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if (!sme_me_mask)
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return;
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wbinvd();
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/*
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* There are limited number of early mapping slots, so map (at most)
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* one page at time.
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*/
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while (size) {
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len = min_t(size_t, sizeof(sme_early_buffer), size);
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/*
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* Create mappings for the current and desired format of
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* the memory. Use a write-protected mapping for the source.
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*/
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src = enc ? early_memremap_decrypted_wp(paddr, len) :
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early_memremap_encrypted_wp(paddr, len);
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dst = enc ? early_memremap_encrypted(paddr, len) :
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early_memremap_decrypted(paddr, len);
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/*
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* If a mapping can't be obtained to perform the operation,
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* then eventual access of that area in the desired mode
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* will cause a crash.
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*/
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BUG_ON(!src || !dst);
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/*
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* Use a temporary buffer, of cache-line multiple size, to
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* avoid data corruption as documented in the APM.
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*/
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memcpy(sme_early_buffer, src, len);
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memcpy(dst, sme_early_buffer, len);
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early_memunmap(dst, len);
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early_memunmap(src, len);
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paddr += len;
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size -= len;
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}
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}
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void __init sme_early_encrypt(resource_size_t paddr, unsigned long size)
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{
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__sme_early_enc_dec(paddr, size, true);
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}
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void __init sme_early_decrypt(resource_size_t paddr, unsigned long size)
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{
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__sme_early_enc_dec(paddr, size, false);
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}
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static void __init __sme_early_map_unmap_mem(void *vaddr, unsigned long size,
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bool map)
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{
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unsigned long paddr = (unsigned long)vaddr - __PAGE_OFFSET;
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pmdval_t pmd_flags, pmd;
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/* Use early_pmd_flags but remove the encryption mask */
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pmd_flags = __sme_clr(early_pmd_flags);
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do {
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pmd = map ? (paddr & PMD_MASK) + pmd_flags : 0;
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__early_make_pgtable((unsigned long)vaddr, pmd);
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vaddr += PMD_SIZE;
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paddr += PMD_SIZE;
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size = (size <= PMD_SIZE) ? 0 : size - PMD_SIZE;
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} while (size);
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__native_flush_tlb();
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}
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void __init sme_unmap_bootdata(char *real_mode_data)
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{
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struct boot_params *boot_data;
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unsigned long cmdline_paddr;
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if (!sme_active())
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return;
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/* Get the command line address before unmapping the real_mode_data */
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boot_data = (struct boot_params *)real_mode_data;
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cmdline_paddr = boot_data->hdr.cmd_line_ptr | ((u64)boot_data->ext_cmd_line_ptr << 32);
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__sme_early_map_unmap_mem(real_mode_data, sizeof(boot_params), false);
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if (!cmdline_paddr)
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return;
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__sme_early_map_unmap_mem(__va(cmdline_paddr), COMMAND_LINE_SIZE, false);
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}
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void __init sme_map_bootdata(char *real_mode_data)
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{
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struct boot_params *boot_data;
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unsigned long cmdline_paddr;
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if (!sme_active())
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return;
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__sme_early_map_unmap_mem(real_mode_data, sizeof(boot_params), true);
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/* Get the command line address after mapping the real_mode_data */
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boot_data = (struct boot_params *)real_mode_data;
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cmdline_paddr = boot_data->hdr.cmd_line_ptr | ((u64)boot_data->ext_cmd_line_ptr << 32);
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if (!cmdline_paddr)
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return;
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__sme_early_map_unmap_mem(__va(cmdline_paddr), COMMAND_LINE_SIZE, true);
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}
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void __init sme_early_init(void)
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{
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unsigned int i;
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if (!sme_me_mask)
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return;
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early_pmd_flags = __sme_set(early_pmd_flags);
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__supported_pte_mask = __sme_set(__supported_pte_mask);
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/* Update the protection map with memory encryption mask */
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for (i = 0; i < ARRAY_SIZE(protection_map); i++)
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protection_map[i] = pgprot_encrypted(protection_map[i]);
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if (sev_active())
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swiotlb_force = SWIOTLB_FORCE;
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}
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static void __init __set_clr_pte_enc(pte_t *kpte, int level, bool enc)
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{
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pgprot_t old_prot, new_prot;
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unsigned long pfn, pa, size;
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pte_t new_pte;
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switch (level) {
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case PG_LEVEL_4K:
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pfn = pte_pfn(*kpte);
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old_prot = pte_pgprot(*kpte);
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break;
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case PG_LEVEL_2M:
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pfn = pmd_pfn(*(pmd_t *)kpte);
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old_prot = pmd_pgprot(*(pmd_t *)kpte);
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break;
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case PG_LEVEL_1G:
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pfn = pud_pfn(*(pud_t *)kpte);
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old_prot = pud_pgprot(*(pud_t *)kpte);
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break;
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default:
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return;
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}
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new_prot = old_prot;
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if (enc)
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pgprot_val(new_prot) |= _PAGE_ENC;
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else
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pgprot_val(new_prot) &= ~_PAGE_ENC;
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/* If prot is same then do nothing. */
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if (pgprot_val(old_prot) == pgprot_val(new_prot))
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return;
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pa = pfn << page_level_shift(level);
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size = page_level_size(level);
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/*
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* We are going to perform in-place en-/decryption and change the
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* physical page attribute from C=1 to C=0 or vice versa. Flush the
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* caches to ensure that data gets accessed with the correct C-bit.
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*/
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clflush_cache_range(__va(pa), size);
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/* Encrypt/decrypt the contents in-place */
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if (enc)
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sme_early_encrypt(pa, size);
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else
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sme_early_decrypt(pa, size);
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/* Change the page encryption mask. */
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new_pte = pfn_pte(pfn, new_prot);
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set_pte_atomic(kpte, new_pte);
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}
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static int __init early_set_memory_enc_dec(unsigned long vaddr,
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unsigned long size, bool enc)
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{
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unsigned long vaddr_end, vaddr_next;
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unsigned long psize, pmask;
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int split_page_size_mask;
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int level, ret;
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pte_t *kpte;
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vaddr_next = vaddr;
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vaddr_end = vaddr + size;
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for (; vaddr < vaddr_end; vaddr = vaddr_next) {
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kpte = lookup_address(vaddr, &level);
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if (!kpte || pte_none(*kpte)) {
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ret = 1;
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goto out;
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}
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if (level == PG_LEVEL_4K) {
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__set_clr_pte_enc(kpte, level, enc);
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vaddr_next = (vaddr & PAGE_MASK) + PAGE_SIZE;
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continue;
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}
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psize = page_level_size(level);
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pmask = page_level_mask(level);
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/*
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* Check whether we can change the large page in one go.
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* We request a split when the address is not aligned and
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* the number of pages to set/clear encryption bit is smaller
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* than the number of pages in the large page.
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*/
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if (vaddr == (vaddr & pmask) &&
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((vaddr_end - vaddr) >= psize)) {
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__set_clr_pte_enc(kpte, level, enc);
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vaddr_next = (vaddr & pmask) + psize;
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continue;
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}
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/*
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* The virtual address is part of a larger page, create the next
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* level page table mapping (4K or 2M). If it is part of a 2M
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* page then we request a split of the large page into 4K
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* chunks. A 1GB large page is split into 2M pages, resp.
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*/
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if (level == PG_LEVEL_2M)
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split_page_size_mask = 0;
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else
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split_page_size_mask = 1 << PG_LEVEL_2M;
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/*
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* kernel_physical_mapping_change() does not flush the TLBs, so
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* a TLB flush is required after we exit from the for loop.
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*/
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kernel_physical_mapping_change(__pa(vaddr & pmask),
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__pa((vaddr_end & pmask) + psize),
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split_page_size_mask);
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}
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ret = 0;
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out:
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__flush_tlb_all();
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return ret;
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}
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int __init early_set_memory_decrypted(unsigned long vaddr, unsigned long size)
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{
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return early_set_memory_enc_dec(vaddr, size, false);
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}
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int __init early_set_memory_encrypted(unsigned long vaddr, unsigned long size)
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{
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return early_set_memory_enc_dec(vaddr, size, true);
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}
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/*
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* SME and SEV are very similar but they are not the same, so there are
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* times that the kernel will need to distinguish between SME and SEV. The
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* sme_active() and sev_active() functions are used for this. When a
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* distinction isn't needed, the mem_encrypt_active() function can be used.
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*
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* The trampoline code is a good example for this requirement. Before
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* paging is activated, SME will access all memory as decrypted, but SEV
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* will access all memory as encrypted. So, when APs are being brought
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* up under SME the trampoline area cannot be encrypted, whereas under SEV
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* the trampoline area must be encrypted.
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*/
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bool sme_active(void)
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{
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return sme_me_mask && !sev_enabled;
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}
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bool sev_active(void)
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{
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return sme_me_mask && sev_enabled;
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}
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/* Override for DMA direct allocation check - ARCH_HAS_FORCE_DMA_UNENCRYPTED */
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bool force_dma_unencrypted(struct device *dev)
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{
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/*
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* For SEV, all DMA must be to unencrypted addresses.
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*/
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if (sev_active())
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return true;
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/*
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* For SME, all DMA must be to unencrypted addresses if the
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* device does not support DMA to addresses that include the
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* encryption mask.
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*/
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if (sme_active()) {
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u64 dma_enc_mask = DMA_BIT_MASK(__ffs64(sme_me_mask));
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u64 dma_dev_mask = min_not_zero(dev->coherent_dma_mask,
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dev->bus_dma_limit);
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if (dma_dev_mask <= dma_enc_mask)
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return true;
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}
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return false;
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}
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/* Architecture __weak replacement functions */
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void __init mem_encrypt_free_decrypted_mem(void)
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{
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unsigned long vaddr, vaddr_end, npages;
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int r;
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vaddr = (unsigned long)__start_bss_decrypted_unused;
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vaddr_end = (unsigned long)__end_bss_decrypted;
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npages = (vaddr_end - vaddr) >> PAGE_SHIFT;
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/*
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* The unused memory range was mapped decrypted, change the encryption
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* attribute from decrypted to encrypted before freeing it.
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*/
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if (mem_encrypt_active()) {
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r = set_memory_encrypted(vaddr, npages);
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if (r) {
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pr_warn("failed to free unused decrypted pages\n");
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return;
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}
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}
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free_init_pages("unused decrypted", vaddr, vaddr_end);
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}
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void __init mem_encrypt_init(void)
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{
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if (!sme_me_mask)
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return;
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/* Call into SWIOTLB to update the SWIOTLB DMA buffers */
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swiotlb_update_mem_attributes();
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/*
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* With SEV, we need to unroll the rep string I/O instructions.
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*/
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if (sev_active())
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static_branch_enable(&sev_enable_key);
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pr_info("AMD %s active\n",
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sev_active() ? "Secure Encrypted Virtualization (SEV)"
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: "Secure Memory Encryption (SME)");
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}
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