mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 00:46:43 +07:00
6f6a657c99
Hyper-V provides direct tlb flush function which helps L1 Hypervisor to handle Hyper-V tlb flush request from L2 guest. Add the function support for VMX. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Signed-off-by: Tianyu Lan <Tianyu.Lan@microsoft.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
206 lines
5.7 KiB
C
206 lines
5.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_VMX_EVMCS_H
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#define __KVM_X86_VMX_EVMCS_H
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#include <linux/jump_label.h>
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#include <asm/hyperv-tlfs.h>
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#include <asm/mshyperv.h>
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#include <asm/vmx.h>
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#include "capabilities.h"
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#include "vmcs.h"
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struct vmcs_config;
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DECLARE_STATIC_KEY_FALSE(enable_evmcs);
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#define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
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#define KVM_EVMCS_VERSION 1
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/*
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* Enlightened VMCSv1 doesn't support these:
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*
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* POSTED_INTR_NV = 0x00000002,
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* GUEST_INTR_STATUS = 0x00000810,
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* APIC_ACCESS_ADDR = 0x00002014,
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* POSTED_INTR_DESC_ADDR = 0x00002016,
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* EOI_EXIT_BITMAP0 = 0x0000201c,
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* EOI_EXIT_BITMAP1 = 0x0000201e,
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* EOI_EXIT_BITMAP2 = 0x00002020,
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* EOI_EXIT_BITMAP3 = 0x00002022,
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* GUEST_PML_INDEX = 0x00000812,
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* PML_ADDRESS = 0x0000200e,
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* VM_FUNCTION_CONTROL = 0x00002018,
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* EPTP_LIST_ADDRESS = 0x00002024,
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* VMREAD_BITMAP = 0x00002026,
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* VMWRITE_BITMAP = 0x00002028,
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*
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* TSC_MULTIPLIER = 0x00002032,
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* PLE_GAP = 0x00004020,
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* PLE_WINDOW = 0x00004022,
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* VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
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* GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
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* HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
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*
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* Currently unsupported in KVM:
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* GUEST_IA32_RTIT_CTL = 0x00002814,
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*/
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#define EVMCS1_UNSUPPORTED_PINCTRL (PIN_BASED_POSTED_INTR | \
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PIN_BASED_VMX_PREEMPTION_TIMER)
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#define EVMCS1_UNSUPPORTED_2NDEXEC \
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(SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | \
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SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | \
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SECONDARY_EXEC_APIC_REGISTER_VIRT | \
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SECONDARY_EXEC_ENABLE_PML | \
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SECONDARY_EXEC_ENABLE_VMFUNC | \
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SECONDARY_EXEC_SHADOW_VMCS | \
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SECONDARY_EXEC_TSC_SCALING | \
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SECONDARY_EXEC_PAUSE_LOOP_EXITING)
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#define EVMCS1_UNSUPPORTED_VMEXIT_CTRL (VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
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#define EVMCS1_UNSUPPORTED_VMENTRY_CTRL (VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
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#define EVMCS1_UNSUPPORTED_VMFUNC (VMX_VMFUNC_EPTP_SWITCHING)
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#if IS_ENABLED(CONFIG_HYPERV)
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struct evmcs_field {
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u16 offset;
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u16 clean_field;
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};
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extern const struct evmcs_field vmcs_field_to_evmcs_1[];
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extern const unsigned int nr_evmcs_1_fields;
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#define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
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static __always_inline int get_evmcs_offset(unsigned long field,
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u16 *clean_field)
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{
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unsigned int index = ROL16(field, 6);
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const struct evmcs_field *evmcs_field;
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if (unlikely(index >= nr_evmcs_1_fields)) {
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WARN_ONCE(1, "KVM: accessing unsupported EVMCS field %lx\n",
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field);
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return -ENOENT;
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}
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evmcs_field = &vmcs_field_to_evmcs_1[index];
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if (clean_field)
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*clean_field = evmcs_field->clean_field;
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return evmcs_field->offset;
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}
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#undef ROL16
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static inline void evmcs_write64(unsigned long field, u64 value)
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{
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u16 clean_field;
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int offset = get_evmcs_offset(field, &clean_field);
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if (offset < 0)
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return;
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*(u64 *)((char *)current_evmcs + offset) = value;
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current_evmcs->hv_clean_fields &= ~clean_field;
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}
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static inline void evmcs_write32(unsigned long field, u32 value)
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{
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u16 clean_field;
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int offset = get_evmcs_offset(field, &clean_field);
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if (offset < 0)
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return;
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*(u32 *)((char *)current_evmcs + offset) = value;
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current_evmcs->hv_clean_fields &= ~clean_field;
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}
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static inline void evmcs_write16(unsigned long field, u16 value)
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{
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u16 clean_field;
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int offset = get_evmcs_offset(field, &clean_field);
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if (offset < 0)
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return;
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*(u16 *)((char *)current_evmcs + offset) = value;
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current_evmcs->hv_clean_fields &= ~clean_field;
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}
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static inline u64 evmcs_read64(unsigned long field)
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{
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int offset = get_evmcs_offset(field, NULL);
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if (offset < 0)
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return 0;
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return *(u64 *)((char *)current_evmcs + offset);
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}
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static inline u32 evmcs_read32(unsigned long field)
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{
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int offset = get_evmcs_offset(field, NULL);
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if (offset < 0)
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return 0;
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return *(u32 *)((char *)current_evmcs + offset);
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}
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static inline u16 evmcs_read16(unsigned long field)
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{
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int offset = get_evmcs_offset(field, NULL);
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if (offset < 0)
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return 0;
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return *(u16 *)((char *)current_evmcs + offset);
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}
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static inline void evmcs_touch_msr_bitmap(void)
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{
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if (unlikely(!current_evmcs))
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return;
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if (current_evmcs->hv_enlightenments_control.msr_bitmap)
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current_evmcs->hv_clean_fields &=
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~HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP;
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}
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static inline void evmcs_load(u64 phys_addr)
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{
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struct hv_vp_assist_page *vp_ap =
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hv_get_vp_assist_page(smp_processor_id());
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if (current_evmcs->hv_enlightenments_control.nested_flush_hypercall)
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vp_ap->nested_control.features.directhypercall = 1;
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vp_ap->current_nested_vmcs = phys_addr;
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vp_ap->enlighten_vmentry = 1;
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}
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void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf);
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#else /* !IS_ENABLED(CONFIG_HYPERV) */
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static inline void evmcs_write64(unsigned long field, u64 value) {}
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static inline void evmcs_write32(unsigned long field, u32 value) {}
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static inline void evmcs_write16(unsigned long field, u16 value) {}
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static inline u64 evmcs_read64(unsigned long field) { return 0; }
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static inline u32 evmcs_read32(unsigned long field) { return 0; }
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static inline u16 evmcs_read16(unsigned long field) { return 0; }
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static inline void evmcs_load(u64 phys_addr) {}
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static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config *vmcs_conf) {}
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static inline void evmcs_touch_msr_bitmap(void) {}
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#endif /* IS_ENABLED(CONFIG_HYPERV) */
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bool nested_enlightened_vmentry(struct kvm_vcpu *vcpu, u64 *evmcs_gpa);
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uint16_t nested_get_evmcs_version(struct kvm_vcpu *vcpu);
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int nested_enable_evmcs(struct kvm_vcpu *vcpu,
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uint16_t *vmcs_version);
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#endif /* __KVM_X86_VMX_EVMCS_H */
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