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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e67172f579
This patch adds the initialisation calls for the SMP support on the PB11MPCore platform. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
257 lines
6.1 KiB
C
257 lines
6.1 KiB
C
/*
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* linux/arch/arm/mach-realview/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/arch/board-eb.h>
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#include <asm/arch/board-pb11mp.h>
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#include <asm/arch/scu.h>
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extern void realview_secondary_startup(void);
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/*
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* control for which core is the next to come out of the secondary
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* boot "holding pen"
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*/
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volatile int __cpuinitdata pen_release = -1;
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static unsigned int __init get_core_count(void)
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{
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unsigned int ncores;
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void __iomem *scu_base = 0;
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if (machine_is_realview_eb() && core_tile_eb11mp())
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scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
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else if (machine_is_realview_pb11mp())
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scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
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if (scu_base) {
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ncores = __raw_readl(scu_base + SCU_CONFIG);
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ncores = (ncores & 0x03) + 1;
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} else
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ncores = 1;
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return ncores;
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}
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/*
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* Setup the SCU
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*/
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static void scu_enable(void)
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{
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u32 scu_ctrl;
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void __iomem *scu_base;
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if (machine_is_realview_eb() && core_tile_eb11mp())
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scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
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else if (machine_is_realview_pb11mp())
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scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
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else
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BUG();
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scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
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scu_ctrl |= 1;
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__raw_writel(scu_ctrl, scu_base + SCU_CTRL);
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}
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static DEFINE_SPINLOCK(boot_lock);
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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/*
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* the primary core may have used a "cross call" soft interrupt
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* to get this processor out of WFI in the BootMonitor - make
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* sure that we are no longer being sent this soft interrupt
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*/
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smp_cross_call_done(cpumask_of_cpu(cpu));
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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if (machine_is_realview_eb() && core_tile_eb11mp())
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gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
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else if (machine_is_realview_pb11mp())
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gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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pen_release = -1;
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smp_wmb();
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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/*
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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pen_release = cpu;
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flush_cache_all();
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/*
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* XXX
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*
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* This is a later addition to the booting protocol: the
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* bootMonitor now puts secondary cores into WFI, so
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* poke_milo() no longer gets the cores moving; we need
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* to send a soft interrupt to wake the secondary core.
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* Use smp_cross_call() for this, since there's little
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* point duplicating the code here
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*/
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smp_cross_call(cpumask_of_cpu(cpu));
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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static void __init poke_milo(void)
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{
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extern void secondary_startup(void);
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/* nobody is to be released from the pen yet */
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pen_release = -1;
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/*
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* write the address of secondary startup into the system-wide
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* flags register, then clear the bottom two bits, which is what
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* BootMonitor is waiting for
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*/
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#if 1
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#define REALVIEW_SYS_FLAGSS_OFFSET 0x30
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__raw_writel(virt_to_phys(realview_secondary_startup),
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__io_address(REALVIEW_SYS_BASE) +
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REALVIEW_SYS_FLAGSS_OFFSET);
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#define REALVIEW_SYS_FLAGSC_OFFSET 0x34
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__raw_writel(3,
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__io_address(REALVIEW_SYS_BASE) +
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REALVIEW_SYS_FLAGSC_OFFSET);
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#endif
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mb();
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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void __init smp_init_cpus(void)
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{
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unsigned int i, ncores = get_core_count();
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for (i = 0; i < ncores; i++)
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cpu_set(i, cpu_possible_map);
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}
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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unsigned int ncores = get_core_count();
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unsigned int cpu = smp_processor_id();
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int i;
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/* sanity check */
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if (ncores == 0) {
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printk(KERN_ERR
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"Realview: strange CM count of 0? Default to 1\n");
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ncores = 1;
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}
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if (ncores > NR_CPUS) {
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printk(KERN_WARNING
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"Realview: no. of cores (%d) greater than configured "
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"maximum of %d - clipping\n",
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ncores, NR_CPUS);
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ncores = NR_CPUS;
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}
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smp_store_cpu_info(cpu);
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/*
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* are we trying to boot more cores than exist?
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*/
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if (max_cpus > ncores)
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max_cpus = ncores;
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#ifdef CONFIG_LOCAL_TIMERS
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/*
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* Enable the local timer for primary CPU. If the device is
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* dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
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* realview_timer_init
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*/
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if ((machine_is_realview_eb() && core_tile_eb11mp()) ||
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machine_is_realview_pb11mp())
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local_timer_setup(cpu);
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#endif
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/*
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* Initialise the present map, which describes the set of CPUs
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* actually populated at the present time.
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*/
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for (i = 0; i < max_cpus; i++)
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cpu_set(i, cpu_present_map);
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/*
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* Initialise the SCU if there are more than one CPU and let
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* them know where to start. Note that, on modern versions of
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* MILO, the "poke" doesn't actually do anything until each
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* individual core is sent a soft interrupt to get it out of
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* WFI
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*/
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if (max_cpus > 1) {
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scu_enable();
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poke_milo();
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}
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}
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