mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 10:18:34 +07:00
47ec7f09bc
The cookie tracking in dmaengine expects all submissions completed in order. Some DMA devices like Intel DSA can complete submissions out of order, especially if configured with a work queue sharing multiple DMA engines. Add a status DMA_OUT_OF_ORDER that tx_status can be returned for those DMA devices. The user should use callbacks to track the completion rather than the DMA cookie. This would address the issue of dmatest complaining that descriptors are "busy" when the cookie count goes backwards due to out of order completion. Add DMA_COMPLETION_NO_ORDER DMA capability to allow the driver to flag the device's ability to complete operations out of order. Reported-by: Swathi Kovvuri <swathi.kovvuri@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Tested-by: Swathi Kovvuri <swathi.kovvuri@intel.com> Link: https://lore.kernel.org/r/158939557151.20335.12404113976045569870.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
219 lines
5.3 KiB
C
219 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/device.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/dmaengine.h>
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#include <uapi/linux/idxd.h>
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#include "../dmaengine.h"
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#include "registers.h"
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#include "idxd.h"
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static inline struct idxd_wq *to_idxd_wq(struct dma_chan *c)
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{
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return container_of(c, struct idxd_wq, dma_chan);
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}
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void idxd_dma_complete_txd(struct idxd_desc *desc,
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enum idxd_complete_type comp_type)
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{
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struct dma_async_tx_descriptor *tx;
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struct dmaengine_result res;
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int complete = 1;
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if (desc->completion->status == DSA_COMP_SUCCESS)
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res.result = DMA_TRANS_NOERROR;
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else if (desc->completion->status)
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res.result = DMA_TRANS_WRITE_FAILED;
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else if (comp_type == IDXD_COMPLETE_ABORT)
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res.result = DMA_TRANS_ABORTED;
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else
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complete = 0;
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tx = &desc->txd;
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if (complete && tx->cookie) {
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dma_cookie_complete(tx);
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dma_descriptor_unmap(tx);
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dmaengine_desc_get_callback_invoke(tx, &res);
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tx->callback = NULL;
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tx->callback_result = NULL;
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}
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}
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static void op_flag_setup(unsigned long flags, u32 *desc_flags)
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{
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*desc_flags = IDXD_OP_FLAG_CRAV | IDXD_OP_FLAG_RCR;
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if (flags & DMA_PREP_INTERRUPT)
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*desc_flags |= IDXD_OP_FLAG_RCI;
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}
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static inline void set_completion_address(struct idxd_desc *desc,
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u64 *compl_addr)
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{
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*compl_addr = desc->compl_dma;
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}
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static inline void idxd_prep_desc_common(struct idxd_wq *wq,
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struct dsa_hw_desc *hw, char opcode,
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u64 addr_f1, u64 addr_f2, u64 len,
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u64 compl, u32 flags)
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{
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struct idxd_device *idxd = wq->idxd;
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hw->flags = flags;
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hw->opcode = opcode;
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hw->src_addr = addr_f1;
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hw->dst_addr = addr_f2;
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hw->xfer_size = len;
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hw->priv = !!(wq->type == IDXD_WQT_KERNEL);
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hw->completion_addr = compl;
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/*
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* Descriptor completion vectors are 1-8 for MSIX. We will round
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* robin through the 8 vectors.
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*/
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wq->vec_ptr = (wq->vec_ptr % idxd->num_wq_irqs) + 1;
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hw->int_handle = wq->vec_ptr;
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}
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static struct dma_async_tx_descriptor *
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idxd_dma_submit_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
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dma_addr_t dma_src, size_t len, unsigned long flags)
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{
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struct idxd_wq *wq = to_idxd_wq(c);
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u32 desc_flags;
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struct idxd_device *idxd = wq->idxd;
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struct idxd_desc *desc;
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if (wq->state != IDXD_WQ_ENABLED)
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return NULL;
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if (len > idxd->max_xfer_bytes)
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return NULL;
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op_flag_setup(flags, &desc_flags);
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desc = idxd_alloc_desc(wq, IDXD_OP_BLOCK);
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if (IS_ERR(desc))
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return NULL;
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idxd_prep_desc_common(wq, desc->hw, DSA_OPCODE_MEMMOVE,
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dma_src, dma_dest, len, desc->compl_dma,
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desc_flags);
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desc->txd.flags = flags;
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return &desc->txd;
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}
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static int idxd_dma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct idxd_wq *wq = to_idxd_wq(chan);
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struct device *dev = &wq->idxd->pdev->dev;
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idxd_wq_get(wq);
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dev_dbg(dev, "%s: client_count: %d\n", __func__,
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idxd_wq_refcount(wq));
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return 0;
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}
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static void idxd_dma_free_chan_resources(struct dma_chan *chan)
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{
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struct idxd_wq *wq = to_idxd_wq(chan);
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struct device *dev = &wq->idxd->pdev->dev;
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idxd_wq_put(wq);
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dev_dbg(dev, "%s: client_count: %d\n", __func__,
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idxd_wq_refcount(wq));
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}
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static enum dma_status idxd_dma_tx_status(struct dma_chan *dma_chan,
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dma_cookie_t cookie,
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struct dma_tx_state *txstate)
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{
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return DMA_OUT_OF_ORDER;
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}
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/*
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* issue_pending() does not need to do anything since tx_submit() does the job
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* already.
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*/
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static void idxd_dma_issue_pending(struct dma_chan *dma_chan)
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{
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}
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dma_cookie_t idxd_dma_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct dma_chan *c = tx->chan;
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struct idxd_wq *wq = to_idxd_wq(c);
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dma_cookie_t cookie;
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int rc;
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struct idxd_desc *desc = container_of(tx, struct idxd_desc, txd);
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cookie = dma_cookie_assign(tx);
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rc = idxd_submit_desc(wq, desc);
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if (rc < 0) {
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idxd_free_desc(wq, desc);
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return rc;
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}
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return cookie;
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}
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static void idxd_dma_release(struct dma_device *device)
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{
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}
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int idxd_register_dma_device(struct idxd_device *idxd)
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{
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struct dma_device *dma = &idxd->dma_dev;
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INIT_LIST_HEAD(&dma->channels);
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dma->dev = &idxd->pdev->dev;
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dma_cap_set(DMA_COMPLETION_NO_ORDER, dma->cap_mask);
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dma->device_release = idxd_dma_release;
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if (idxd->hw.opcap.bits[0] & IDXD_OPCAP_MEMMOVE) {
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dma_cap_set(DMA_MEMCPY, dma->cap_mask);
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dma->device_prep_dma_memcpy = idxd_dma_submit_memcpy;
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}
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dma->device_tx_status = idxd_dma_tx_status;
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dma->device_issue_pending = idxd_dma_issue_pending;
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dma->device_alloc_chan_resources = idxd_dma_alloc_chan_resources;
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dma->device_free_chan_resources = idxd_dma_free_chan_resources;
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return dma_async_device_register(&idxd->dma_dev);
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}
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void idxd_unregister_dma_device(struct idxd_device *idxd)
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{
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dma_async_device_unregister(&idxd->dma_dev);
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}
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int idxd_register_dma_channel(struct idxd_wq *wq)
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{
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struct idxd_device *idxd = wq->idxd;
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struct dma_device *dma = &idxd->dma_dev;
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struct dma_chan *chan = &wq->dma_chan;
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int rc;
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memset(&wq->dma_chan, 0, sizeof(struct dma_chan));
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chan->device = dma;
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list_add_tail(&chan->device_node, &dma->channels);
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rc = dma_async_device_channel_register(dma, chan);
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if (rc < 0)
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return rc;
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return 0;
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}
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void idxd_unregister_dma_channel(struct idxd_wq *wq)
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{
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dma_async_device_channel_unregister(&wq->idxd->dma_dev, &wq->dma_chan);
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}
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