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0997a2662f
Peter suggested that using the exclusive mode in perf could avoid some
problems with bad scheduling of groups. Exclusive is implemented in the
kernel, but wasn't exposed by the perf tool, so hard to use without
custom low level API users.
Add support for marking groups or events with :e for exclusive in the
perf tool. The implementation is basically the same as the existing
pinned attribute.
Committer testing:
# perf test "parse event"
6: Parse event definition strings : Ok
# perf test -v "parse event" |& grep :u*e
running test 56 'instructions:uep'
running test 57 '{cycles,cache-misses,branch-misses}:e'
#
#
# grep "model name" -m1 /proc/cpuinfo
model name : AMD Ryzen 9 3900X 12-Core Processor
#
# perf stat -a -e '{cycles,cache-misses,branch-misses}:e' sleep 1
Performance counter stats for 'system wide':
<not counted> cycles (0.00%)
<not counted> cache-misses (0.00%)
<not counted> branch-misses (0.00%)
1.001269893 seconds time elapsed
Some events weren't counted. Try disabling the NMI watchdog:
echo 0 > /proc/sys/kernel/nmi_watchdog
perf stat ...
echo 1 > /proc/sys/kernel/nmi_watchdog
# echo 0 > /proc/sys/kernel/nmi_watchdog
# perf stat -a -e '{cycles,cache-misses,branch-misses}:e' sleep 1
Performance counter stats for 'system wide':
1,298,663,141 cycles
30,962,215 cache-misses
5,325,150 branch-misses
1.001474934 seconds time elapsed
#
# The output for asking for precise events on AMD needs to improve, it
# supposedly works only for system wide or per CPU
#
# perf stat -a -e '{cycles,cache-misses,branch-misses}:uep' sleep 1
Error:
The sys_perf_event_open() syscall returned with 22 (Invalid argument) for event (cycles).
/bin/dmesg | grep -i perf may provide additional information.
# perf stat -a -e '{cycles,cache-misses,branch-misses}:ue' sleep 1
Performance counter stats for 'system wide':
746,363,126 cycles
16,881,611 cache-misses
2,871,259 branch-misses
1.001636066 seconds time elapsed
#
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Acked-by: Jiri Olsa <jolsa@kernel.org>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lore.kernel.org/lkml/20201014144255.22699-1-andi@firstfloor.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
316 lines
10 KiB
Plaintext
316 lines
10 KiB
Plaintext
perf-list(1)
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============
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NAME
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----
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perf-list - List all symbolic event types
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SYNOPSIS
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--------
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[verse]
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'perf list' [--no-desc] [--long-desc]
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[hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob]
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DESCRIPTION
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-----------
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This command displays the symbolic event types which can be selected in the
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various perf commands with the -e option.
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OPTIONS
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-------
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-d::
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--desc::
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Print extra event descriptions. (default)
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--no-desc::
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Don't print descriptions.
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-v::
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--long-desc::
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Print longer event descriptions.
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--debug::
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Enable debugging output.
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--details::
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Print how named events are resolved internally into perf events, and also
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any extra expressions computed by perf stat.
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--deprecated::
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Print deprecated events. By default the deprecated events are hidden.
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[[EVENT_MODIFIERS]]
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EVENT MODIFIERS
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---------------
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Events can optionally have a modifier by appending a colon and one or
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more modifiers. Modifiers allow the user to restrict the events to be
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counted. The following modifiers exist:
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u - user-space counting
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k - kernel counting
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h - hypervisor counting
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I - non idle counting
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G - guest counting (in KVM guests)
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H - host counting (not in KVM guests)
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p - precise level
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P - use maximum detected precise level
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S - read sample value (PERF_SAMPLE_READ)
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D - pin the event to the PMU
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W - group is weak and will fallback to non-group if not schedulable,
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e - group or event are exclusive and do not share the PMU
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The 'p' modifier can be used for specifying how precise the instruction
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address should be. The 'p' modifier can be specified multiple times:
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0 - SAMPLE_IP can have arbitrary skid
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1 - SAMPLE_IP must have constant skid
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2 - SAMPLE_IP requested to have 0 skid
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3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
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sample shadowing effects.
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For Intel systems precise event sampling is implemented with PEBS
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which supports up to precise-level 2, and precise level 3 for
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some special cases
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On AMD systems it is implemented using IBS (up to precise-level 2).
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The precise modifier works with event types 0x76 (cpu-cycles, CPU
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clocks not halted) and 0xC1 (micro-ops retired). Both events map to
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IBS execution sampling (IBS op) with the IBS Op Counter Control bit
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(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
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Manual Volume 2: System Programming, 13.3 Instruction-Based
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Sampling). Examples to use IBS:
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perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
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perf record -a -e r076:p ... # same as -e cpu-cycles:p
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perf record -a -e r0C1:p ... # use ibs op counting micro-ops
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RAW HARDWARE EVENT DESCRIPTOR
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-----------------------------
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Even when an event is not available in a symbolic form within perf right now,
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it can be encoded in a per processor specific way.
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For instance For x86 CPUs NNN represents the raw register encoding with the
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layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
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of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
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Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
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Note: Only the following bit fields can be set in x86 counter
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registers: event, umask, edge, inv, cmask. Esp. guest/host only and
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OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
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MODIFIERS>>.
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Example:
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If the Intel docs for a QM720 Core i7 describe an event as:
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Event Umask Event Mask
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Num. Value Mnemonic Description Comment
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A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
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delivered by loop stream detector invert to count
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cycles
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raw encoding of 0x1A8 can be used:
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perf stat -e r1a8 -a sleep 1
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perf record -e r1a8 ...
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It's also possible to use pmu syntax:
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perf record -e r1a8 -a sleep 1
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perf record -e cpu/r1a8/ ...
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perf record -e cpu/r0x1a8/ ...
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You should refer to the processor specific documentation for getting these
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details. Some of them are referenced in the SEE ALSO section below.
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ARBITRARY PMUS
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--------------
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perf also supports an extended syntax for specifying raw parameters
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to PMUs. Using this typically requires looking up the specific event
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in the CPU vendor specific documentation.
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The available PMUs and their raw parameters can be listed with
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ls /sys/devices/*/format
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For example the raw event "LSD.UOPS" core pmu event above could
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be specified as
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perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ...
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or using extended name syntax
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perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ...
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PER SOCKET PMUS
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---------------
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Some PMUs are not associated with a core, but with a whole CPU socket.
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Events on these PMUs generally cannot be sampled, but only counted globally
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with perf stat -a. They can be bound to one logical CPU, but will measure
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all the CPUs in the same socket.
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This example measures memory bandwidth every second
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on the first memory controller on socket 0 of a Intel Xeon system
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perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
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Each memory controller has its own PMU. Measuring the complete system
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bandwidth would require specifying all imc PMUs (see perf list output),
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and adding the values together. To simplify creation of multiple events,
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prefix and glob matching is supported in the PMU name, and the prefix
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'uncore_' is also ignored when performing the match. So the command above
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can be expanded to all memory controllers by using the syntaxes:
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perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ...
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perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ...
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This example measures the combined core power every second
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perf stat -I 1000 -e power/energy-cores/ -a
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ACCESS RESTRICTIONS
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-------------------
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For non root users generally only context switched PMU events are available.
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This is normally only the events in the cpu PMU, the predefined events
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like cycles and instructions and some software events.
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Other PMUs and global measurements are normally root only.
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Some event qualifiers, such as "any", are also root only.
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This can be overridden by setting the kernel.perf_event_paranoid
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sysctl to -1, which allows non root to use these events.
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For accessing trace point events perf needs to have read access to
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/sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed
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setting.
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TRACING
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-------
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Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
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that allows low overhead execution tracing. These are described in a separate
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intel-pt.txt document.
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PARAMETERIZED EVENTS
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--------------------
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Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
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example:
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hv_gpci/dtbp_ptitc,phys_processor_idx=?/
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This means that when provided as an event, a value for '?' must
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also be supplied. For example:
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perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
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EVENT QUALIFIERS:
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It is also possible to add extra qualifiers to an event:
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percore:
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Sums up the event counts for all hardware threads in a core, e.g.:
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perf stat -e cpu/event=0,umask=0x3,percore=1/
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EVENT GROUPS
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------------
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Perf supports time based multiplexing of events, when the number of events
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active exceeds the number of hardware performance counters. Multiplexing
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can cause measurement errors when the workload changes its execution
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profile.
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When metrics are computed using formulas from event counts, it is useful to
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ensure some events are always measured together as a group to minimize multiplexing
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errors. Event groups can be specified using { }.
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perf stat -e '{instructions,cycles}' ...
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The number of available performance counters depend on the CPU. A group
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cannot contain more events than available counters.
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For example Intel Core CPUs typically have four generic performance counters
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for the core, plus three fixed counters for instructions, cycles and
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ref-cycles. Some special events have restrictions on which counter they
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can schedule, and may not support multiple instances in a single group.
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When too many events are specified in the group some of them will not
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be measured.
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Globally pinned events can limit the number of counters available for
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other groups. On x86 systems, the NMI watchdog pins a counter by default.
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The nmi watchdog can be disabled as root with
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echo 0 > /proc/sys/kernel/nmi_watchdog
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Events from multiple different PMUs cannot be mixed in a group, with
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some exceptions for software events.
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LEADER SAMPLING
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---------------
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perf also supports group leader sampling using the :S specifier.
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perf record -e '{cycles,instructions}:S' ...
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perf report --group
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Normally all events in an event group sample, but with :S only
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the first event (the leader) samples, and it only reads the values of the
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other events in the group.
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However, in the case AUX area events (e.g. Intel PT or CoreSight), the AUX
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area event must be the leader, so then the second event samples, not the first.
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OPTIONS
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-------
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Without options all known events will be listed.
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To limit the list use:
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. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
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. 'sw' or 'software' to list software events such as context switches, etc.
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. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
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. 'tracepoint' to list all tracepoint events, alternatively use
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'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
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block, etc.
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. 'pmu' to print the kernel supplied PMU events.
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. 'sdt' to list all Statically Defined Tracepoint events.
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. 'metric' to list metrics
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. 'metricgroup' to list metricgroups with metrics.
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. If none of the above is matched, it will apply the supplied glob to all
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events, printing the ones that match.
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. As a last resort, it will do a substring search in all event names.
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One or more types can be used at the same time, listing the events for the
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types specified.
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Support raw format:
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. '--raw-dump', shows the raw-dump of all the events.
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. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
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a certain kind of events.
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SEE ALSO
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--------
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linkperf:perf-stat[1], linkperf:perf-top[1],
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linkperf:perf-record[1],
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http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
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http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]
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