mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 18:45:25 +07:00
f7ad082cac
A33 has the same "Security System" crypto engine as A10/A20, but with a separate reset control. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
176 lines
4.9 KiB
Plaintext
176 lines
4.9 KiB
Plaintext
/*
|
|
* Copyright 2014 Chen-Yu Tsai
|
|
*
|
|
* Chen-Yu Tsai <wens@csie.org>
|
|
*
|
|
* This file is dual-licensed: you can use it either under the terms
|
|
* of the GPL or the X11 license, at your option. Note that this dual
|
|
* licensing only applies to this file, and not this project as a
|
|
* whole.
|
|
*
|
|
* a) This file is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of the
|
|
* License, or (at your option) any later version.
|
|
*
|
|
* This file is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* Or, alternatively,
|
|
*
|
|
* b) Permission is hereby granted, free of charge, to any person
|
|
* obtaining a copy of this software and associated documentation
|
|
* files (the "Software"), to deal in the Software without
|
|
* restriction, including without limitation the rights to use,
|
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
|
* sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following
|
|
* conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be
|
|
* included in all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
* OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include "sun8i-a23-a33.dtsi"
|
|
|
|
/ {
|
|
cpus {
|
|
cpu@2 {
|
|
compatible = "arm,cortex-a7";
|
|
device_type = "cpu";
|
|
reg = <2>;
|
|
};
|
|
|
|
cpu@3 {
|
|
compatible = "arm,cortex-a7";
|
|
device_type = "cpu";
|
|
reg = <3>;
|
|
};
|
|
};
|
|
|
|
memory {
|
|
reg = <0x40000000 0x80000000>;
|
|
};
|
|
|
|
clocks {
|
|
/* Dummy clock for pll11 (DDR1) until actually implemented */
|
|
pll11: pll11_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0>;
|
|
clock-output-names = "pll11";
|
|
};
|
|
|
|
ahb1_gates: clk@01c20060 {
|
|
#clock-cells = <1>;
|
|
compatible = "allwinner,sun8i-a33-ahb1-gates-clk";
|
|
reg = <0x01c20060 0x8>;
|
|
clocks = <&ahb1>;
|
|
clock-indices = <1>, <5>,
|
|
<6>, <8>, <9>,
|
|
<10>, <13>, <14>,
|
|
<19>, <20>,
|
|
<21>, <24>, <26>,
|
|
<29>, <32>, <36>,
|
|
<40>, <44>, <46>,
|
|
<52>, <53>,
|
|
<54>, <57>,
|
|
<58>;
|
|
clock-output-names = "ahb1_mipidsi", "ahb1_ss",
|
|
"ahb1_dma","ahb1_mmc0", "ahb1_mmc1",
|
|
"ahb1_mmc2", "ahb1_nand", "ahb1_sdram",
|
|
"ahb1_hstimer", "ahb1_spi0",
|
|
"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
|
|
"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
|
|
"ahb1_csi", "ahb1_be", "ahb1_fe",
|
|
"ahb1_gpu", "ahb1_msgbox",
|
|
"ahb1_spinlock", "ahb1_drc",
|
|
"ahb1_sat";
|
|
};
|
|
|
|
ss_clk: clk@01c2009c {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
|
reg = <0x01c2009c 0x4>;
|
|
clocks = <&osc24M>, <&pll6 0>;
|
|
clock-output-names = "ss";
|
|
};
|
|
|
|
mbus_clk: clk@01c2015c {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun8i-a23-mbus-clk";
|
|
reg = <0x01c2015c 0x4>;
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5>, <&pll11>;
|
|
clock-output-names = "mbus";
|
|
};
|
|
};
|
|
|
|
soc@01c00000 {
|
|
crypto: crypto-engine@01c15000 {
|
|
compatible = "allwinner,sun4i-a10-crypto";
|
|
reg = <0x01c15000 0x1000>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 5>, <&ss_clk>;
|
|
clock-names = "ahb", "mod";
|
|
resets = <&ahb1_rst 5>;
|
|
reset-names = "ahb";
|
|
};
|
|
|
|
usb_otg: usb@01c19000 {
|
|
compatible = "allwinner,sun8i-a33-musb";
|
|
reg = <0x01c19000 0x0400>;
|
|
clocks = <&ahb1_gates 24>;
|
|
resets = <&ahb1_rst 24>;
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mc";
|
|
phys = <&usbphy 0>;
|
|
phy-names = "usb";
|
|
extcon = <&usbphy 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbphy: phy@01c19400 {
|
|
compatible = "allwinner,sun8i-a33-usb-phy";
|
|
reg = <0x01c19400 0x14>,
|
|
<0x01c1a800 0x4>;
|
|
reg-names = "phy_ctrl",
|
|
"pmu1";
|
|
clocks = <&usb_clk 8>,
|
|
<&usb_clk 9>;
|
|
clock-names = "usb0_phy",
|
|
"usb1_phy";
|
|
resets = <&usb_clk 0>,
|
|
<&usb_clk 1>;
|
|
reset-names = "usb0_reset",
|
|
"usb1_reset";
|
|
status = "disabled";
|
|
#phy-cells = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&pio {
|
|
compatible = "allwinner,sun8i-a33-pinctrl";
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
uart0_pins_b: uart0@1 {
|
|
allwinner,pins = "PB0", "PB1";
|
|
allwinner,function = "uart0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
};
|