mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 04:36:40 +07:00
7fb20f9e90
The BPF helper bpf_trace_printk() no longer uses trace_printk();
it is now triggers a dedicated trace event. Hence the described
warning is no longer present, so remove the discussion of it as
it may confuse people.
Fixes: ac5a72ea5c ("bpf: Use dedicated bpf_trace_printk event instead of trace_printk()")
Signed-off-by: Alan Maguire <alan.maguire@oracle.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Link: https://lore.kernel.org/bpf/1596801029-32395-1-git-send-email-alan.maguire@oracle.com
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==============
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BPF Design Q&A
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==============
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BPF extensibility and applicability to networking, tracing, security
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in the linux kernel and several user space implementations of BPF
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virtual machine led to a number of misunderstanding on what BPF actually is.
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This short QA is an attempt to address that and outline a direction
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of where BPF is heading long term.
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.. contents::
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:local:
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:depth: 3
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Questions and Answers
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=====================
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Q: Is BPF a generic instruction set similar to x64 and arm64?
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-------------------------------------------------------------
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A: NO.
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Q: Is BPF a generic virtual machine ?
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-------------------------------------
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A: NO.
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BPF is generic instruction set *with* C calling convention.
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-----------------------------------------------------------
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Q: Why C calling convention was chosen?
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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A: Because BPF programs are designed to run in the linux kernel
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which is written in C, hence BPF defines instruction set compatible
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with two most used architectures x64 and arm64 (and takes into
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consideration important quirks of other architectures) and
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defines calling convention that is compatible with C calling
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convention of the linux kernel on those architectures.
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Q: Can multiple return values be supported in the future?
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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A: NO. BPF allows only register R0 to be used as return value.
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Q: Can more than 5 function arguments be supported in the future?
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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A: NO. BPF calling convention only allows registers R1-R5 to be used
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as arguments. BPF is not a standalone instruction set.
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(unlike x64 ISA that allows msft, cdecl and other conventions)
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Q: Can BPF programs access instruction pointer or return address?
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-----------------------------------------------------------------
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A: NO.
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Q: Can BPF programs access stack pointer ?
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------------------------------------------
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A: NO.
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Only frame pointer (register R10) is accessible.
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From compiler point of view it's necessary to have stack pointer.
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For example, LLVM defines register R11 as stack pointer in its
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BPF backend, but it makes sure that generated code never uses it.
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Q: Does C-calling convention diminishes possible use cases?
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-----------------------------------------------------------
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A: YES.
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BPF design forces addition of major functionality in the form
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of kernel helper functions and kernel objects like BPF maps with
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seamless interoperability between them. It lets kernel call into
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BPF programs and programs call kernel helpers with zero overhead,
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as all of them were native C code. That is particularly the case
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for JITed BPF programs that are indistinguishable from
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native kernel C code.
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Q: Does it mean that 'innovative' extensions to BPF code are disallowed?
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------------------------------------------------------------------------
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A: Soft yes.
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At least for now, until BPF core has support for
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bpf-to-bpf calls, indirect calls, loops, global variables,
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jump tables, read-only sections, and all other normal constructs
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that C code can produce.
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Q: Can loops be supported in a safe way?
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----------------------------------------
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A: It's not clear yet.
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BPF developers are trying to find a way to
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support bounded loops.
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Q: What are the verifier limits?
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--------------------------------
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A: The only limit known to the user space is BPF_MAXINSNS (4096).
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It's the maximum number of instructions that the unprivileged bpf
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program can have. The verifier has various internal limits.
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Like the maximum number of instructions that can be explored during
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program analysis. Currently, that limit is set to 1 million.
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Which essentially means that the largest program can consist
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of 1 million NOP instructions. There is a limit to the maximum number
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of subsequent branches, a limit to the number of nested bpf-to-bpf
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calls, a limit to the number of the verifier states per instruction,
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a limit to the number of maps used by the program.
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All these limits can be hit with a sufficiently complex program.
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There are also non-numerical limits that can cause the program
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to be rejected. The verifier used to recognize only pointer + constant
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expressions. Now it can recognize pointer + bounded_register.
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bpf_lookup_map_elem(key) had a requirement that 'key' must be
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a pointer to the stack. Now, 'key' can be a pointer to map value.
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The verifier is steadily getting 'smarter'. The limits are
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being removed. The only way to know that the program is going to
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be accepted by the verifier is to try to load it.
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The bpf development process guarantees that the future kernel
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versions will accept all bpf programs that were accepted by
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the earlier versions.
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Instruction level questions
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---------------------------
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Q: LD_ABS and LD_IND instructions vs C code
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Q: How come LD_ABS and LD_IND instruction are present in BPF whereas
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C code cannot express them and has to use builtin intrinsics?
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A: This is artifact of compatibility with classic BPF. Modern
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networking code in BPF performs better without them.
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See 'direct packet access'.
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Q: BPF instructions mapping not one-to-one to native CPU
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Q: It seems not all BPF instructions are one-to-one to native CPU.
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For example why BPF_JNE and other compare and jumps are not cpu-like?
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A: This was necessary to avoid introducing flags into ISA which are
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impossible to make generic and efficient across CPU architectures.
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Q: Why BPF_DIV instruction doesn't map to x64 div?
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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A: Because if we picked one-to-one relationship to x64 it would have made
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it more complicated to support on arm64 and other archs. Also it
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needs div-by-zero runtime check.
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Q: Why there is no BPF_SDIV for signed divide operation?
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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A: Because it would be rarely used. llvm errors in such case and
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prints a suggestion to use unsigned divide instead.
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Q: Why BPF has implicit prologue and epilogue?
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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A: Because architectures like sparc have register windows and in general
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there are enough subtle differences between architectures, so naive
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store return address into stack won't work. Another reason is BPF has
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to be safe from division by zero (and legacy exception path
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of LD_ABS insn). Those instructions need to invoke epilogue and
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return implicitly.
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Q: Why BPF_JLT and BPF_JLE instructions were not introduced in the beginning?
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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A: Because classic BPF didn't have them and BPF authors felt that compiler
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workaround would be acceptable. Turned out that programs lose performance
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due to lack of these compare instructions and they were added.
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These two instructions is a perfect example what kind of new BPF
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instructions are acceptable and can be added in the future.
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These two already had equivalent instructions in native CPUs.
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New instructions that don't have one-to-one mapping to HW instructions
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will not be accepted.
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Q: BPF 32-bit subregister requirements
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Q: BPF 32-bit subregisters have a requirement to zero upper 32-bits of BPF
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registers which makes BPF inefficient virtual machine for 32-bit
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CPU architectures and 32-bit HW accelerators. Can true 32-bit registers
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be added to BPF in the future?
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A: NO.
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But some optimizations on zero-ing the upper 32 bits for BPF registers are
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available, and can be leveraged to improve the performance of JITed BPF
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programs for 32-bit architectures.
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Starting with version 7, LLVM is able to generate instructions that operate
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on 32-bit subregisters, provided the option -mattr=+alu32 is passed for
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compiling a program. Furthermore, the verifier can now mark the
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instructions for which zero-ing the upper bits of the destination register
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is required, and insert an explicit zero-extension (zext) instruction
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(a mov32 variant). This means that for architectures without zext hardware
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support, the JIT back-ends do not need to clear the upper bits for
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subregisters written by alu32 instructions or narrow loads. Instead, the
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back-ends simply need to support code generation for that mov32 variant,
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and to overwrite bpf_jit_needs_zext() to make it return "true" (in order to
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enable zext insertion in the verifier).
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Note that it is possible for a JIT back-end to have partial hardware
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support for zext. In that case, if verifier zext insertion is enabled,
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it could lead to the insertion of unnecessary zext instructions. Such
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instructions could be removed by creating a simple peephole inside the JIT
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back-end: if one instruction has hardware support for zext and if the next
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instruction is an explicit zext, then the latter can be skipped when doing
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the code generation.
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Q: Does BPF have a stable ABI?
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------------------------------
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A: YES. BPF instructions, arguments to BPF programs, set of helper
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functions and their arguments, recognized return codes are all part
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of ABI. However there is one specific exception to tracing programs
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which are using helpers like bpf_probe_read() to walk kernel internal
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data structures and compile with kernel internal headers. Both of these
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kernel internals are subject to change and can break with newer kernels
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such that the program needs to be adapted accordingly.
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Q: How much stack space a BPF program uses?
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-------------------------------------------
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A: Currently all program types are limited to 512 bytes of stack
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space, but the verifier computes the actual amount of stack used
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and both interpreter and most JITed code consume necessary amount.
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Q: Can BPF be offloaded to HW?
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------------------------------
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A: YES. BPF HW offload is supported by NFP driver.
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Q: Does classic BPF interpreter still exist?
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--------------------------------------------
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A: NO. Classic BPF programs are converted into extend BPF instructions.
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Q: Can BPF call arbitrary kernel functions?
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-------------------------------------------
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A: NO. BPF programs can only call a set of helper functions which
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is defined for every program type.
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Q: Can BPF overwrite arbitrary kernel memory?
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---------------------------------------------
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A: NO.
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Tracing bpf programs can *read* arbitrary memory with bpf_probe_read()
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and bpf_probe_read_str() helpers. Networking programs cannot read
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arbitrary memory, since they don't have access to these helpers.
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Programs can never read or write arbitrary memory directly.
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Q: Can BPF overwrite arbitrary user memory?
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-------------------------------------------
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A: Sort-of.
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Tracing BPF programs can overwrite the user memory
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of the current task with bpf_probe_write_user(). Every time such
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program is loaded the kernel will print warning message, so
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this helper is only useful for experiments and prototypes.
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Tracing BPF programs are root only.
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Q: New functionality via kernel modules?
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----------------------------------------
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Q: Can BPF functionality such as new program or map types, new
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helpers, etc be added out of kernel module code?
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A: NO.
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