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0a51826c6e
I finally found out how the 4 management route slots are supposed to be used, but.. it's not worth it. The description from the comment I've just deleted in this commit is still true: when more than 1 management slot is active at the same time, the switch will match frames incoming [from the CPU port] on the lowest numbered management slot that matches the frame's DMAC. My issue was that one was not supposed to statically assign each port a slot. Yes, there are 4 slots and also 4 non-CPU ports, but that is a mere coincidence. Instead, the switch can be used like this: every management frame gets a slot at the right of the most recently assigned slot: Send mgmt frame 1 through S0: S0 x x x Send mgmt frame 2 through S1: S0 S1 x x Send mgmt frame 3 through S2: S0 S1 S2 x Send mgmt frame 4 through S3: S0 S1 S2 S3 The difference compared to the old usage is that the transmission of frames 1-4 doesn't need to wait until the completion of the management route. It is safe to use a slot to the right of the most recently used one, because by protocol nobody will program a slot to your left and "steal" your route towards the correct egress port. So there is a potential throughput benefit here. But mgmt frame 5 has no more free slot to use, so it has to wait until _all_ of S0, S1, S2, S3 are full, in order to use S0 again. And that's actually exactly the problem: I was looking for something that would bring more predictable transmission latency, but this is exactly the opposite: 3 out of 4 frames would be transmitted quicker, but the 4th would draw the short straw and have a worse worst-case latency than before. Useless. Things are made even worse by PTP TX timestamping, which is something I won't go deeply into here. Suffice to say that the fact there is a driver-level lock on the SPI bus offsets any potential throughput gains that parallelism might bring. So there's no going back to the multi-slot scheme, remove the "mgmt_slot" variable from sja1105_port and the dummy static assignment made at probe time. While passing by, also remove the assignment to casc_port altogether. Don't pretend that we support cascaded setups. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
62 lines
1.9 KiB
C
62 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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* Copyright (c) 2019, Vladimir Oltean <olteanv@gmail.com>
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*/
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/* Included by drivers/net/dsa/sja1105/sja1105.h and net/dsa/tag_sja1105.c */
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#ifndef _NET_DSA_SJA1105_H
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#define _NET_DSA_SJA1105_H
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#include <linux/skbuff.h>
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#include <linux/etherdevice.h>
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#include <net/dsa.h>
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#define ETH_P_SJA1105 ETH_P_DSA_8021Q
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#define ETH_P_SJA1105_META 0x0008
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/* IEEE 802.3 Annex 57A: Slow Protocols PDUs (01:80:C2:xx:xx:xx) */
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#define SJA1105_LINKLOCAL_FILTER_A 0x0180C2000000ull
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#define SJA1105_LINKLOCAL_FILTER_A_MASK 0xFFFFFF000000ull
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/* IEEE 1588 Annex F: Transport of PTP over Ethernet (01:1B:19:xx:xx:xx) */
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#define SJA1105_LINKLOCAL_FILTER_B 0x011B19000000ull
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#define SJA1105_LINKLOCAL_FILTER_B_MASK 0xFFFFFF000000ull
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/* Source and Destination MAC of follow-up meta frames.
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* Whereas the choice of SMAC only affects the unique identification of the
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* switch as sender of meta frames, the DMAC must be an address that is present
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* in the DSA master port's multicast MAC filter.
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* 01-80-C2-00-00-0E is a good choice for this, as all profiles of IEEE 1588
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* over L2 use this address for some purpose already.
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*/
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#define SJA1105_META_SMAC 0x222222222222ull
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#define SJA1105_META_DMAC 0x0180C200000Eull
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#define SJA1105_HWTS_RX_EN 0
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/* Global tagger data: each struct sja1105_port has a reference to
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* the structure defined in struct sja1105_private.
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*/
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struct sja1105_tagger_data {
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struct sk_buff *stampable_skb;
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/* Protects concurrent access to the meta state machine
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* from taggers running on multiple ports on SMP systems
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*/
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spinlock_t meta_lock;
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unsigned long state;
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};
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struct sja1105_skb_cb {
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u32 meta_tstamp;
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};
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#define SJA1105_SKB_CB(skb) \
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((struct sja1105_skb_cb *)DSA_SKB_CB_PRIV(skb))
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struct sja1105_port {
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struct sja1105_tagger_data *data;
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struct dsa_port *dp;
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bool hwts_tx_en;
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};
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#endif /* _NET_DSA_SJA1105_H */
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