linux_dsm_epyc7002/drivers/gpu/drm/amd
Hersen Wu 09ed6ba43e drm/amdgpu/display: navi1x copy dcn watermark clock settings to smu resume from s3 (v2)
This interface is for dGPU Navi1x. Linux dc-pplib interface depends
 on window driver dc implementation.

 For Navi1x, clock settings of dcn watermarks are fixed. the settings
 should be passed to smu during boot up and resume from s3.
 boot up: dc calculate dcn watermark clock settings within dc_create,
 dcn20_resource_construct, then call pplib functions below to pass
 the settings to smu:
 smu_set_watermarks_for_clock_ranges
 smu_set_watermarks_table
 navi10_set_watermarks_table
 smu_write_watermarks_table

 For Renoir, clock settings of dcn watermark are also fixed values.
 dc has implemented different flow for window driver:
 dc_hardware_init / dc_set_power_state
 dcn10_init_hw
 notify_wm_ranges
 set_wm_ranges

 For Linux
 smu_set_watermarks_for_clock_ranges
 renoir_set_watermarks_table
 smu_write_watermarks_table

 dc_hardware_init -> amdgpu_dm_init
 dc_set_power_state --> dm_resume

 therefore, linux dc-pplib interface of navi10/12/14 is different
 from that of Renoir.

v2: add missing unlock in error case

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-03-05 09:42:08 -05:00
..
acp drm/amdgpu: fix license on Kconfig and Makefiles 2019-12-11 15:22:08 -05:00
amdgpu drm/amdgpu: disable 3D pipe 1 on Navi1x 2020-03-05 09:41:55 -05:00
amdkfd drm/amdkfd: Fix a bug in SDMA RLC queue counting under HWS mode 2020-02-04 10:32:41 -05:00
display drm/amdgpu/display: navi1x copy dcn watermark clock settings to smu resume from s3 (v2) 2020-03-05 09:42:08 -05:00
include amdgpu/gmc_v9: save/restore sdpif regs during S3 2020-02-25 11:30:42 -05:00
powerplay drm/amd/powerplay: map mclk to fclk for COMBINATIONAL_BYPASS case 2020-03-05 09:42:08 -05:00