mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 16:50:53 +07:00
3f0ea7645a
Add offset & mask fields to struct powerdomain In case of AM33xx family of devices, there is no consistency between PWRSTCTRL & PWRSTST register offsers in PRM space, for example - PRM_XXX PWRSTCTRL PWRSTST ======================================= PRM_PER_MOD: 0x0C, 0x08 PRM_WKUP_MOD: 0x04, 0x08 PRM_MPU_MOD: 0x00, 0x04 PRM_DEVICE_MOD: NA, NA And also, there is no consistency between bit-offsets inside PWRSTCTRL & PWRSTST register, for example - PRM_XXX LOGICRET MEMON MEMRET ======================================= GFX_PWRCTRL: 2, 17, 6 PER_PWRCTRL: 3, 25, 29 MPU_PWRCTRL: 2, 18, 22 WKUP_PWRCTRL: 3, NA, NA This means, we need to maintain and pass on all this information in powerdomain handle; so adding fields for, - PWRSTCTRL/ST register offset - Logic retention state mask - mem_on/ret/pwrst/retst mask Currently, this fields is only applicable and used for AM33XX devices. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: this patch is a combination of "Add offset & mask fields to struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx: Add powerdomain & PRM support"; updated for 3.5] Signed-off-by: Paul Walmsley <paul@pwsan.com>
186 lines
5.6 KiB
C
186 lines
5.6 KiB
C
/*
|
|
* AM33XX Power domain data
|
|
*
|
|
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation version 2.
|
|
*
|
|
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
|
* kind, whether express or implied; without even the implied warranty
|
|
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/init.h>
|
|
|
|
#include "powerdomain.h"
|
|
#include "prcm-common.h"
|
|
#include "prm-regbits-33xx.h"
|
|
#include "prm33xx.h"
|
|
|
|
static struct powerdomain gfx_33xx_pwrdm = {
|
|
.name = "gfx_pwrdm",
|
|
.voltdm = { .name = "core" },
|
|
.prcm_offs = AM33XX_PRM_GFX_MOD,
|
|
.pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
|
|
.pwrstst_offs = AM33XX_PM_GFX_PWRSTST_OFFSET,
|
|
.pwrsts = PWRSTS_OFF_RET_ON,
|
|
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
|
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
|
.banks = 1,
|
|
.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
|
|
.mem_on_mask = {
|
|
[0] = AM33XX_GFX_MEM_ONSTATE_MASK, /* gfx_mem */
|
|
},
|
|
.mem_ret_mask = {
|
|
[0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
|
|
},
|
|
.mem_pwrst_mask = {
|
|
[0] = AM33XX_GFX_MEM_STATEST_MASK, /* gfx_mem */
|
|
},
|
|
.mem_retst_mask = {
|
|
[0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
|
|
},
|
|
.pwrsts_mem_ret = {
|
|
[0] = PWRSTS_OFF_RET, /* gfx_mem */
|
|
},
|
|
.pwrsts_mem_on = {
|
|
[0] = PWRSTS_ON, /* gfx_mem */
|
|
},
|
|
};
|
|
|
|
static struct powerdomain rtc_33xx_pwrdm = {
|
|
.name = "rtc_pwrdm",
|
|
.voltdm = { .name = "rtc" },
|
|
.prcm_offs = AM33XX_PRM_RTC_MOD,
|
|
.pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
|
|
.pwrstst_offs = AM33XX_PM_RTC_PWRSTST_OFFSET,
|
|
.pwrsts = PWRSTS_ON,
|
|
.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
|
|
};
|
|
|
|
static struct powerdomain wkup_33xx_pwrdm = {
|
|
.name = "wkup_pwrdm",
|
|
.voltdm = { .name = "core" },
|
|
.prcm_offs = AM33XX_PRM_WKUP_MOD,
|
|
.pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
|
|
.pwrstst_offs = AM33XX_PM_WKUP_PWRSTST_OFFSET,
|
|
.pwrsts = PWRSTS_ON,
|
|
.logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
|
|
};
|
|
|
|
static struct powerdomain per_33xx_pwrdm = {
|
|
.name = "per_pwrdm",
|
|
.voltdm = { .name = "core" },
|
|
.prcm_offs = AM33XX_PRM_PER_MOD,
|
|
.pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET,
|
|
.pwrstst_offs = AM33XX_PM_PER_PWRSTST_OFFSET,
|
|
.pwrsts = PWRSTS_OFF_RET_ON,
|
|
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
|
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
|
.banks = 3,
|
|
.logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
|
|
.mem_on_mask = {
|
|
[0] = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */
|
|
[1] = AM33XX_PER_MEM_ONSTATE_MASK, /* per_mem */
|
|
[2] = AM33XX_RAM_MEM_ONSTATE_MASK, /* ram_mem */
|
|
},
|
|
.mem_ret_mask = {
|
|
[0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
|
|
[1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
|
|
[2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
|
|
},
|
|
.mem_pwrst_mask = {
|
|
[0] = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */
|
|
[1] = AM33XX_PER_MEM_STATEST_MASK, /* per_mem */
|
|
[2] = AM33XX_RAM_MEM_STATEST_MASK, /* ram_mem */
|
|
},
|
|
.mem_retst_mask = {
|
|
[0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
|
|
[1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
|
|
[2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
|
|
},
|
|
.pwrsts_mem_ret = {
|
|
[0] = PWRSTS_OFF_RET, /* pruss_mem */
|
|
[1] = PWRSTS_OFF_RET, /* per_mem */
|
|
[2] = PWRSTS_OFF_RET, /* ram_mem */
|
|
},
|
|
.pwrsts_mem_on = {
|
|
[0] = PWRSTS_ON, /* pruss_mem */
|
|
[1] = PWRSTS_ON, /* per_mem */
|
|
[2] = PWRSTS_ON, /* ram_mem */
|
|
},
|
|
};
|
|
|
|
static struct powerdomain mpu_33xx_pwrdm = {
|
|
.name = "mpu_pwrdm",
|
|
.voltdm = { .name = "mpu" },
|
|
.prcm_offs = AM33XX_PRM_MPU_MOD,
|
|
.pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
|
|
.pwrstst_offs = AM33XX_PM_MPU_PWRSTST_OFFSET,
|
|
.pwrsts = PWRSTS_OFF_RET_ON,
|
|
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
|
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
|
.banks = 3,
|
|
.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
|
|
.mem_on_mask = {
|
|
[0] = AM33XX_MPU_L1_ONSTATE_MASK, /* mpu_l1 */
|
|
[1] = AM33XX_MPU_L2_ONSTATE_MASK, /* mpu_l2 */
|
|
[2] = AM33XX_MPU_RAM_ONSTATE_MASK, /* mpu_ram */
|
|
},
|
|
.mem_ret_mask = {
|
|
[0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
|
|
[1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
|
|
[2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
|
|
},
|
|
.mem_pwrst_mask = {
|
|
[0] = AM33XX_MPU_L1_STATEST_MASK, /* mpu_l1 */
|
|
[1] = AM33XX_MPU_L2_STATEST_MASK, /* mpu_l2 */
|
|
[2] = AM33XX_MPU_RAM_STATEST_MASK, /* mpu_ram */
|
|
},
|
|
.mem_retst_mask = {
|
|
[0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
|
|
[1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
|
|
[2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
|
|
},
|
|
.pwrsts_mem_ret = {
|
|
[0] = PWRSTS_OFF_RET, /* mpu_l1 */
|
|
[1] = PWRSTS_OFF_RET, /* mpu_l2 */
|
|
[2] = PWRSTS_OFF_RET, /* mpu_ram */
|
|
},
|
|
.pwrsts_mem_on = {
|
|
[0] = PWRSTS_ON, /* mpu_l1 */
|
|
[1] = PWRSTS_ON, /* mpu_l2 */
|
|
[2] = PWRSTS_ON, /* mpu_ram */
|
|
},
|
|
};
|
|
|
|
static struct powerdomain cefuse_33xx_pwrdm = {
|
|
.name = "cefuse_pwrdm",
|
|
.voltdm = { .name = "core" },
|
|
.prcm_offs = AM33XX_PRM_CEFUSE_MOD,
|
|
.pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
|
|
.pwrstst_offs = AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
};
|
|
|
|
static struct powerdomain *powerdomains_am33xx[] __initdata = {
|
|
&gfx_33xx_pwrdm,
|
|
&rtc_33xx_pwrdm,
|
|
&wkup_33xx_pwrdm,
|
|
&per_33xx_pwrdm,
|
|
&mpu_33xx_pwrdm,
|
|
&cefuse_33xx_pwrdm,
|
|
NULL,
|
|
};
|
|
|
|
void __init am33xx_powerdomains_init(void)
|
|
{
|
|
pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
|
|
pwrdm_register_pwrdms(powerdomains_am33xx);
|
|
pwrdm_complete_init();
|
|
}
|