mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-24 19:19:37 +07:00
3d464aadef
This patch adds defines for 10M and EEE 100M link modes, which are supported by A2. 10M support is added in this patch series. EEE is out of scope, but will be added in a follow-up series. Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* aQuantia Corporation Network Driver
|
|
* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
|
|
*/
|
|
|
|
/* File aq_common.h: Basic includes for all files in project. */
|
|
|
|
#ifndef AQ_COMMON_H
|
|
#define AQ_COMMON_H
|
|
|
|
#include <linux/etherdevice.h>
|
|
#include <linux/pci.h>
|
|
#include <linux/if_vlan.h>
|
|
#include "aq_cfg.h"
|
|
#include "aq_utils.h"
|
|
|
|
#define PCI_VENDOR_ID_AQUANTIA 0x1D6A
|
|
|
|
#define AQ_DEVICE_ID_0001 0x0001
|
|
#define AQ_DEVICE_ID_D100 0xD100
|
|
#define AQ_DEVICE_ID_D107 0xD107
|
|
#define AQ_DEVICE_ID_D108 0xD108
|
|
#define AQ_DEVICE_ID_D109 0xD109
|
|
|
|
#define AQ_DEVICE_ID_AQC100 0x00B1
|
|
#define AQ_DEVICE_ID_AQC107 0x07B1
|
|
#define AQ_DEVICE_ID_AQC108 0x08B1
|
|
#define AQ_DEVICE_ID_AQC109 0x09B1
|
|
#define AQ_DEVICE_ID_AQC111 0x11B1
|
|
#define AQ_DEVICE_ID_AQC112 0x12B1
|
|
|
|
#define AQ_DEVICE_ID_AQC100S 0x80B1
|
|
#define AQ_DEVICE_ID_AQC107S 0x87B1
|
|
#define AQ_DEVICE_ID_AQC108S 0x88B1
|
|
#define AQ_DEVICE_ID_AQC109S 0x89B1
|
|
#define AQ_DEVICE_ID_AQC111S 0x91B1
|
|
#define AQ_DEVICE_ID_AQC112S 0x92B1
|
|
|
|
#define AQ_DEVICE_ID_AQC113DEV 0x00C0
|
|
#define AQ_DEVICE_ID_AQC113CS 0x94C0
|
|
#define AQ_DEVICE_ID_AQC114CS 0x93C0
|
|
#define AQ_DEVICE_ID_AQC113 0x04C0
|
|
#define AQ_DEVICE_ID_AQC113C 0x14C0
|
|
#define AQ_DEVICE_ID_AQC115C 0x12C0
|
|
|
|
#define HW_ATL_NIC_NAME "Marvell (aQuantia) AQtion 10Gbit Network Adapter"
|
|
|
|
#define AQ_HWREV_ANY 0
|
|
#define AQ_HWREV_1 1
|
|
#define AQ_HWREV_2 2
|
|
|
|
#define AQ_NIC_RATE_10G BIT(0)
|
|
#define AQ_NIC_RATE_5G BIT(1)
|
|
#define AQ_NIC_RATE_5GSR BIT(2)
|
|
#define AQ_NIC_RATE_2GS BIT(3)
|
|
#define AQ_NIC_RATE_1G BIT(4)
|
|
#define AQ_NIC_RATE_100M BIT(5)
|
|
#define AQ_NIC_RATE_10M BIT(6)
|
|
|
|
#define AQ_NIC_RATE_EEE_10G BIT(7)
|
|
#define AQ_NIC_RATE_EEE_5G BIT(8)
|
|
#define AQ_NIC_RATE_EEE_2GS BIT(9)
|
|
#define AQ_NIC_RATE_EEE_1G BIT(10)
|
|
#define AQ_NIC_RATE_EEE_100M BIT(11)
|
|
|
|
#endif /* AQ_COMMON_H */
|