mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-07 06:26:39 +07:00
010dc8af8f
Two problems exist in the current i.MX5 pm suspend/resume and idle functions. The first is the current i.MX5 suspend routine will call tzic_enable_wake(1) to set wake source, this will set all enabled irq as wake source rather than those wake capable. The second is i.MX5 idle will call mx5_cpu_lp_set() to prepare enter low power mode, but it forgets to call wfi instruction to enter this mode. To fix these two problems, using generic irq chip pm interface and modify function imx5_idle(). [Tested by Shawn Guo on imx51 babbage board. Tested by Hui Wang on imx51 pdk board.] Signed-off-by: Hui Wang <jason77.wang@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
208 lines
5.4 KiB
C
208 lines
5.4 KiB
C
/*
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* Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <asm/mach/irq.h>
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#include <asm/exception.h>
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#include <mach/hardware.h>
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#include <mach/common.h>
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#include "irq-common.h"
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/*
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*****************************************
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* TZIC Registers *
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*****************************************
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*/
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#define TZIC_INTCNTL 0x0000 /* Control register */
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#define TZIC_INTTYPE 0x0004 /* Controller Type register */
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#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
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#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
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#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
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#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
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#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
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#define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
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#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
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#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
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#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
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#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
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#define TZIC_PND0 0x0D00 /* Pending Register 0 */
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#define TZIC_HIPND(i) (0x0D80+ ((i) << 2)) /* High Priority Pending Register */
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#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
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#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
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#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
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void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
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#define TZIC_NUM_IRQS 128
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#ifdef CONFIG_FIQ
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static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
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{
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unsigned int index, mask, value;
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index = irq >> 5;
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if (unlikely(index >= 4))
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return -EINVAL;
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mask = 1U << (irq & 0x1F);
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value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
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if (type)
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value &= ~mask;
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__raw_writel(value, tzic_base + TZIC_INTSEC0(index));
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return 0;
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}
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#else
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#define tzic_set_irq_fiq NULL
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#endif
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#ifdef CONFIG_PM
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static void tzic_irq_suspend(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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int idx = gc->irq_base >> 5;
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__raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
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}
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static void tzic_irq_resume(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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int idx = gc->irq_base >> 5;
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__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
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tzic_base + TZIC_WAKEUP0(idx));
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}
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#else
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#define tzic_irq_suspend NULL
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#define tzic_irq_resume NULL
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#endif
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static struct mxc_extra_irq tzic_extra_irq = {
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#ifdef CONFIG_FIQ
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.set_irq_fiq = tzic_set_irq_fiq,
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#endif
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};
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static __init void tzic_init_gc(unsigned int irq_start)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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int idx = irq_start >> 5;
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gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
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handle_level_irq);
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gc->private = &tzic_extra_irq;
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gc->wake_enabled = IRQ_MSK(32);
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_disable_reg;
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
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ct->chip.irq_set_wake = irq_gc_set_wake;
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ct->chip.irq_suspend = tzic_irq_suspend;
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ct->chip.irq_resume = tzic_irq_resume;
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ct->regs.disable = TZIC_ENCLEAR0(idx);
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ct->regs.enable = TZIC_ENSET0(idx);
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irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
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}
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asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
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{
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u32 stat;
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int i, irqofs, handled;
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do {
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handled = 0;
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for (i = 0; i < 4; i++) {
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stat = __raw_readl(tzic_base + TZIC_HIPND(i)) &
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__raw_readl(tzic_base + TZIC_INTSEC0(i));
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while (stat) {
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handled = 1;
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irqofs = fls(stat) - 1;
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handle_IRQ(irqofs + i * 32, regs);
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stat &= ~(1 << irqofs);
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}
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}
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} while (handled);
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}
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/*
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* This function initializes the TZIC hardware and disables all the
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* interrupts. It registers the interrupt enable and disable functions
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* to the kernel for each interrupt source.
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*/
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void __init tzic_init_irq(void __iomem *irqbase)
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{
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int i;
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tzic_base = irqbase;
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/* put the TZIC into the reset value with
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* all interrupts disabled
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*/
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i = __raw_readl(tzic_base + TZIC_INTCNTL);
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__raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
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__raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
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__raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
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for (i = 0; i < 4; i++)
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__raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
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/* disable all interrupts */
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for (i = 0; i < 4; i++)
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__raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
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/* all IRQ no FIQ Warning :: No selection */
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for (i = 0; i < TZIC_NUM_IRQS; i += 32)
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tzic_init_gc(i);
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#ifdef CONFIG_FIQ
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/* Initialize FIQ */
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init_FIQ();
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#endif
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pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
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}
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/**
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* tzic_enable_wake() - enable wakeup interrupt
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*
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* @return 0 if successful; non-zero otherwise
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*/
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int tzic_enable_wake(void)
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{
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unsigned int i;
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__raw_writel(1, tzic_base + TZIC_DSMINT);
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if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
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return -EAGAIN;
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for (i = 0; i < 4; i++)
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__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)),
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tzic_base + TZIC_WAKEUP0(i));
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return 0;
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}
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