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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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821dc4dfd9
We used to pass the timer clock directly to mxc_timer_init. We should instead request the correct clock. This is an intermediate step: For now we request the clock in the timer code when NULL is passed as clock. Also, the gpt on some i.MX have an additional ipg clock which can be gated. Request and enable this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
325 lines
8.1 KiB
C
325 lines
8.1 KiB
C
/*
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* linux/arch/arm/plat-mxc/time.c
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*
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* Copyright (C) 2000-2001 Deep Blue Solutions
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
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* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clockchips.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <mach/hardware.h>
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#include <asm/sched_clock.h>
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#include <asm/mach/time.h>
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#include <mach/common.h>
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/*
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* There are 2 versions of the timer hardware on Freescale MXC hardware.
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* Version 1: MX1/MXL, MX21, MX27.
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* Version 2: MX25, MX31, MX35, MX37, MX51
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*/
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/* defines common for all i.MX */
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#define MXC_TCTL 0x00
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#define MXC_TCTL_TEN (1 << 0) /* Enable module */
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#define MXC_TPRER 0x04
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/* MX1, MX21, MX27 */
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#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
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#define MX1_2_TCTL_IRQEN (1 << 4)
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#define MX1_2_TCTL_FRR (1 << 8)
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#define MX1_2_TCMP 0x08
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#define MX1_2_TCN 0x10
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#define MX1_2_TSTAT 0x14
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/* MX21, MX27 */
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#define MX2_TSTAT_CAPT (1 << 1)
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#define MX2_TSTAT_COMP (1 << 0)
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/* MX31, MX35, MX25, MX5 */
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#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
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#define V2_TCTL_CLK_IPG (1 << 6)
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#define V2_TCTL_FRR (1 << 9)
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#define V2_IR 0x0c
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#define V2_TSTAT 0x08
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#define V2_TSTAT_OF1 (1 << 0)
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#define V2_TCN 0x24
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#define V2_TCMP 0x10
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#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
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#define timer_is_v2() (!timer_is_v1())
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static struct clock_event_device clockevent_mxc;
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static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
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static void __iomem *timer_base;
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static inline void gpt_irq_disable(void)
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{
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unsigned int tmp;
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if (timer_is_v2())
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__raw_writel(0, timer_base + V2_IR);
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else {
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tmp = __raw_readl(timer_base + MXC_TCTL);
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__raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
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}
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}
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static inline void gpt_irq_enable(void)
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{
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if (timer_is_v2())
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__raw_writel(1<<0, timer_base + V2_IR);
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else {
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__raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
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timer_base + MXC_TCTL);
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}
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}
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static void gpt_irq_acknowledge(void)
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{
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if (timer_is_v1()) {
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if (cpu_is_mx1())
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__raw_writel(0, timer_base + MX1_2_TSTAT);
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else
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__raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
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timer_base + MX1_2_TSTAT);
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} else if (timer_is_v2())
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__raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
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}
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static void __iomem *sched_clock_reg;
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static u32 notrace mxc_read_sched_clock(void)
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{
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return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
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}
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static int __init mxc_clocksource_init(struct clk *timer_clk)
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{
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unsigned int c = clk_get_rate(timer_clk);
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void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
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sched_clock_reg = reg;
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setup_sched_clock(mxc_read_sched_clock, 32, c);
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return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
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clocksource_mmio_readl_up);
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}
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/* clock event */
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static int mx1_2_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long tcmp;
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tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
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__raw_writel(tcmp, timer_base + MX1_2_TCMP);
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return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
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-ETIME : 0;
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}
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static int v2_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long tcmp;
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tcmp = __raw_readl(timer_base + V2_TCN) + evt;
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__raw_writel(tcmp, timer_base + V2_TCMP);
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return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
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-ETIME : 0;
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}
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#ifdef DEBUG
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static const char *clock_event_mode_label[] = {
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[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
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[CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
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[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
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[CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED"
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};
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#endif /* DEBUG */
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static void mxc_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned long flags;
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/*
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* The timer interrupt generation is disabled at least
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* for enough time to call mxc_set_next_event()
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*/
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local_irq_save(flags);
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/* Disable interrupt in GPT module */
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gpt_irq_disable();
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if (mode != clockevent_mode) {
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/* Set event time into far-far future */
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if (timer_is_v2())
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__raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
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timer_base + V2_TCMP);
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else
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__raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
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timer_base + MX1_2_TCMP);
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/* Clear pending interrupt */
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gpt_irq_acknowledge();
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}
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#ifdef DEBUG
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printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
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clock_event_mode_label[clockevent_mode],
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clock_event_mode_label[mode]);
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#endif /* DEBUG */
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/* Remember timer mode */
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clockevent_mode = mode;
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local_irq_restore(flags);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
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"supported for i.MX\n");
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/*
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* Do not put overhead of interrupt enable/disable into
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* mxc_set_next_event(), the core has about 4 minutes
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* to call mxc_set_next_event() or shutdown clock after
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* mode switching
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*/
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local_irq_save(flags);
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gpt_irq_enable();
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local_irq_restore(flags);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_RESUME:
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/* Left event sources disabled, no more interrupts appear */
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break;
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}
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}
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &clockevent_mxc;
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uint32_t tstat;
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if (timer_is_v2())
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tstat = __raw_readl(timer_base + V2_TSTAT);
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else
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tstat = __raw_readl(timer_base + MX1_2_TSTAT);
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gpt_irq_acknowledge();
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction mxc_timer_irq = {
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.name = "i.MX Timer Tick",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = mxc_timer_interrupt,
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};
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static struct clock_event_device clockevent_mxc = {
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.name = "mxc_timer1",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.set_mode = mxc_set_mode,
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.set_next_event = mx1_2_set_next_event,
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.rating = 200,
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};
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static int __init mxc_clockevent_init(struct clk *timer_clk)
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{
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unsigned int c = clk_get_rate(timer_clk);
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if (timer_is_v2())
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clockevent_mxc.set_next_event = v2_set_next_event;
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clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
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clockevent_mxc.shift);
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clockevent_mxc.max_delta_ns =
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clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
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clockevent_mxc.min_delta_ns =
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clockevent_delta2ns(0xff, &clockevent_mxc);
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clockevent_mxc.cpumask = cpumask_of(0);
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clockevents_register_device(&clockevent_mxc);
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return 0;
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}
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void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
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{
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uint32_t tctl_val;
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struct clk *timer_ipg_clk;
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if (!timer_clk) {
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timer_clk = clk_get_sys("imx-gpt.0", "per");
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if (IS_ERR(timer_clk)) {
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pr_err("i.MX timer: unable to get clk\n");
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return;
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}
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timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
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if (!IS_ERR(timer_ipg_clk))
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clk_prepare_enable(timer_ipg_clk);
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}
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clk_prepare_enable(timer_clk);
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timer_base = base;
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/*
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* Initialise to a known state (all timers off, and timing reset)
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*/
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__raw_writel(0, timer_base + MXC_TCTL);
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__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
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if (timer_is_v2())
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tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
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else
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tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
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__raw_writel(tctl_val, timer_base + MXC_TCTL);
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/* init and register the timer to the framework */
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mxc_clocksource_init(timer_clk);
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mxc_clockevent_init(timer_clk);
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/* Make irqs happen */
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setup_irq(irq, &mxc_timer_irq);
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}
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