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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 05:56:39 +07:00
52585ccd93
Since there're mulitple clock rates in some device controllers, enable clk_set_rate() for this usage. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
87 lines
1.5 KiB
C
87 lines
1.5 KiB
C
/*
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* linux/arch/arm/mach-sa1100/clock.c
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/clkdev.h>
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#include "clock.h"
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static DEFINE_SPINLOCK(clocks_lock);
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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spin_lock_irqsave(&clocks_lock, flags);
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if (clk->enabled++ == 0)
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clk->ops->enable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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if (clk->delay)
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udelay(clk->delay);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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WARN_ON(clk->enabled == 0);
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spin_lock_irqsave(&clocks_lock, flags);
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if (--clk->enabled == 0)
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clk->ops->disable(clk);
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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unsigned long rate;
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rate = clk->rate;
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if (clk->ops->getrate)
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rate = clk->ops->getrate(clk);
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return rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long flags;
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int ret = -EINVAL;
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if (clk->ops->setrate) {
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spin_lock_irqsave(&clocks_lock, flags);
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ret = clk->ops->setrate(clk, rate);
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spin_unlock_irqrestore(&clocks_lock, flags);
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}
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return ret;
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}
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EXPORT_SYMBOL(clk_set_rate);
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void clk_dummy_enable(struct clk *clk)
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{
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}
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void clk_dummy_disable(struct clk *clk)
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{
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}
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const struct clkops clk_dummy_ops = {
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.enable = clk_dummy_enable,
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.disable = clk_dummy_disable,
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};
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struct clk clk_dummy = {
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.ops = &clk_dummy_ops,
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};
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