mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-08 03:17:36 +07:00
281b05392f
These changes are all specific to an soc family or the code for one soc. Lots of work for Tegra3 this time, but also a lot of other platforms. There will be another (smaller) set of soc patches later in the merge window for stuff that has dependencies on external trees or that was sent just before the merge window opened. The asoc tree added a few devices to the i.mx platform, which conflict with other devices added in the same place here. The tegra Makefile conflicts between a number of branches, mostly because of changes regarding localtimer.c, which was removed in the end. Signed-off-by: Arnd Bergmann <arnd@arndb.de> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIVAwUAT24+62CrR//JCVInAQLQBQ/8ClDSFYKTkh3XuzryyO3xkiuuj9wp3/av oEzro6HmSFDeWlqyQYYM9nKn6n3zFyyumG7oHt3OyRwrtV742rMOpTK+/Ntj2lFB xUVwKQfu2gEMHvwca3VoXia/pX7knvedEf9bNjeCznkKxQCKCArK2821/2UDGhwx L3/lD70AhpfK0DInNr6HusnZG2pzCdV1tLXUvgs08I68wL7Ps1TDPOLLyTo9dAgf k+E1cpRNLahyiVUBfnp+n3Dg0T+/7iD6zrR7bE9i/zhv6XUcLPt2K5XqYnPuQvzK sHIG8zROmNWzaIzgwYVpJAofi0SHq1OjvA7RtepOq/pGe5QvB9y1RISlpwzBr6Fh 4yuBkeN/Azk0xSHw5w++8L4y/oSSNhB9OWgIZGChZMW33bnHyiZW9mDFJ/PyWD0F kRl++tTuQqDvT5Wx4DXX8RGekIiFq48+MMx3yJjuGarmVsPEvShQCf8TkBbl/KQY /AEXMJTaVTED0R/q+NOY/r4oMFC4JtAVo1ZtTga+N5cYWQCwI9HVSgAKw84Yc1Hj h9r7XjDhmGYFWMfWe9V5NtFNmXl6tAo66fMzSG6+9k+UEXiF1WrhnzBuks5zFU7z z4WBRL0GmaNBdq58dJoM4lucnuhhQk2m7wz5Lt4o17enw0dAfSXQMstDMnbE7c51 65yZh8o9mxs= =WdYR -----END PGP SIGNATURE----- Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull "ARM: SoC specific updates" from Arnd Bergmann: "These changes are all specific to an soc family or the code for one soc. Lots of work for Tegra3 this time, but also a lot of other platforms. There will be another (smaller) set of soc patches later in the merge window for stuff that has dependencies on external trees or that was sent just before the merge window opened. The asoc tree added a few devices to the i.mx platform, which conflict with other devices added in the same place here. The tegra Makefile conflicts between a number of branches, mostly because of changes regarding localtimer.c, which was removed in the end. Signed-off-by: Arnd Bergmann <arnd@arndb.de>" Fix up some trivial conflicts, including the mentioned Tegra Makefile. * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (51 commits) ARM: EXYNOS: fix cycle count for periodic mode of clock event timers ARM: EXYNOS: add support JPEG ARM: EXYNOS: Add DMC1, allow PPMU access for DMC ARM: SAMSUNG: Correct MIPI-CSIS io memory resource definition ARM: SAMSUNG: fix __init attribute on regarding s3c_set_platdata() ARM: SAMSUNG: Add __init attribute to samsung_bl_set() ARM: S5PV210: Add usb otg phy control ARM: S3C64XX: Add usb otg phy control ARM: EXYNOS: Enable l2 configuration through device tree ARM: EXYNOS: remove useless code to save/restore L2 ARM: EXYNOS: save L2 settings during bootup ARM: S5P: add L2 early resume code ARM: EXYNOS: Add support AFTR mode on EXYNOS4210 ARM: mx35: Setup the AIPS registers ARM: mx5: Use common function for configuring AIPS ARM: mx3: Setup AIPS registers ARM: mx3: Let mx31 and mx35 enter in LPM mode in WFI ARM: defconfig: imx_v6_v7: build in REGULATOR_FIXED_VOLTAGE ARM: imx: update imx_v6_v7_defconfig ARM: tegra: Demote EMC clock inconsistency BUG to WARN ...
520 lines
12 KiB
C
520 lines
12 KiB
C
/*
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* linux/arch/arm/mach-omap2/id.c
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*
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* OMAP2 CPU identification code
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*
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* Copyright (C) 2005 Nokia Corporation
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* Written by Tony Lindgren <tony@atomide.com>
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*
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* Copyright (C) 2009-11 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/cputype.h>
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#include "common.h"
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#include <plat/cpu.h>
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#include <mach/id.h>
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#include "control.h"
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static unsigned int omap_revision;
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static const char *cpu_rev;
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u32 omap_features;
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unsigned int omap_rev(void)
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{
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return omap_revision;
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}
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EXPORT_SYMBOL(omap_rev);
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int omap_type(void)
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{
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u32 val = 0;
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if (cpu_is_omap24xx()) {
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val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
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} else if (cpu_is_am33xx()) {
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val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
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} else if (cpu_is_omap34xx()) {
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val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
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} else if (cpu_is_omap44xx()) {
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val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
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} else {
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pr_err("Cannot detect omap type!\n");
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goto out;
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}
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val &= OMAP2_DEVICETYPE_MASK;
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val >>= 8;
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out:
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return val;
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}
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EXPORT_SYMBOL(omap_type);
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/*----------------------------------------------------------------------------*/
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#define OMAP_TAP_IDCODE 0x0204
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#define OMAP_TAP_DIE_ID_0 0x0218
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#define OMAP_TAP_DIE_ID_1 0x021C
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#define OMAP_TAP_DIE_ID_2 0x0220
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#define OMAP_TAP_DIE_ID_3 0x0224
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#define OMAP_TAP_DIE_ID_44XX_0 0x0200
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#define OMAP_TAP_DIE_ID_44XX_1 0x0208
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#define OMAP_TAP_DIE_ID_44XX_2 0x020c
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#define OMAP_TAP_DIE_ID_44XX_3 0x0210
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#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
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struct omap_id {
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u16 hawkeye; /* Silicon type (Hawkeye id) */
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u8 dev; /* Device type from production_id reg */
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u32 type; /* Combined type id copied to omap_revision */
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};
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/* Register values to detect the OMAP version */
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static struct omap_id omap_ids[] __initdata = {
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{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
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{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
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{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
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{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
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{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
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{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
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};
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static void __iomem *tap_base;
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static u16 tap_prod_id;
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void omap_get_die_id(struct omap_die_id *odi)
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{
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if (cpu_is_omap44xx()) {
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odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
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odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
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odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
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odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
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return;
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}
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odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
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odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
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odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
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odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
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}
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void __init omap2xxx_check_revision(void)
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{
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int i, j;
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u32 idcode, prod_id;
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u16 hawkeye;
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u8 dev_type, rev;
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struct omap_die_id odi;
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idcode = read_tap_reg(OMAP_TAP_IDCODE);
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prod_id = read_tap_reg(tap_prod_id);
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hawkeye = (idcode >> 12) & 0xffff;
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rev = (idcode >> 28) & 0x0f;
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dev_type = (prod_id >> 16) & 0x0f;
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omap_get_die_id(&odi);
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pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
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idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
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pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
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pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
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odi.id_1, (odi.id_1 >> 28) & 0xf);
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pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
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pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
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pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
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prod_id, dev_type);
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/* Check hawkeye ids */
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for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
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if (hawkeye == omap_ids[i].hawkeye)
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break;
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}
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if (i == ARRAY_SIZE(omap_ids)) {
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printk(KERN_ERR "Unknown OMAP CPU id\n");
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return;
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}
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for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
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if (dev_type == omap_ids[j].dev)
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break;
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}
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if (j == ARRAY_SIZE(omap_ids)) {
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printk(KERN_ERR "Unknown OMAP device type. "
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"Handling it as OMAP%04x\n",
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omap_ids[i].type >> 16);
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j = i;
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}
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pr_info("OMAP%04x", omap_rev() >> 16);
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if ((omap_rev() >> 8) & 0x0f)
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pr_info("ES%x", (omap_rev() >> 12) & 0xf);
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pr_info("\n");
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}
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#define OMAP3_SHOW_FEATURE(feat) \
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if (omap3_has_ ##feat()) \
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printk(#feat" ");
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static void __init omap3_cpuinfo(void)
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{
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const char *cpu_name;
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/*
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* OMAP3430 and OMAP3530 are assumed to be same.
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*
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* OMAP3525, OMAP3515 and OMAP3503 can be detected only based
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* on available features. Upon detection, update the CPU id
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* and CPU class bits.
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*/
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if (cpu_is_omap3630()) {
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cpu_name = "OMAP3630";
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} else if (cpu_is_omap3517()) {
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/* AM35xx devices */
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cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
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} else if (cpu_is_ti816x()) {
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cpu_name = "TI816X";
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} else if (cpu_is_am335x()) {
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cpu_name = "AM335X";
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} else if (cpu_is_ti814x()) {
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cpu_name = "TI814X";
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} else if (omap3_has_iva() && omap3_has_sgx()) {
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/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
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cpu_name = "OMAP3430/3530";
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} else if (omap3_has_iva()) {
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cpu_name = "OMAP3525";
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} else if (omap3_has_sgx()) {
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cpu_name = "OMAP3515";
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} else {
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cpu_name = "OMAP3503";
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}
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/* Print verbose information */
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pr_info("%s ES%s (", cpu_name, cpu_rev);
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OMAP3_SHOW_FEATURE(l2cache);
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OMAP3_SHOW_FEATURE(iva);
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OMAP3_SHOW_FEATURE(sgx);
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OMAP3_SHOW_FEATURE(neon);
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OMAP3_SHOW_FEATURE(isp);
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OMAP3_SHOW_FEATURE(192mhz_clk);
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printk(")\n");
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}
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#define OMAP3_CHECK_FEATURE(status,feat) \
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if (((status & OMAP3_ ##feat## _MASK) \
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>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
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omap_features |= OMAP3_HAS_ ##feat; \
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}
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void __init omap3xxx_check_features(void)
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{
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u32 status;
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omap_features = 0;
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status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
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OMAP3_CHECK_FEATURE(status, L2CACHE);
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OMAP3_CHECK_FEATURE(status, IVA);
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OMAP3_CHECK_FEATURE(status, SGX);
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OMAP3_CHECK_FEATURE(status, NEON);
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OMAP3_CHECK_FEATURE(status, ISP);
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if (cpu_is_omap3630())
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omap_features |= OMAP3_HAS_192MHZ_CLK;
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if (cpu_is_omap3430() || cpu_is_omap3630())
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omap_features |= OMAP3_HAS_IO_WAKEUP;
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if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
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omap_rev() == OMAP3430_REV_ES3_1_2)
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omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
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omap_features |= OMAP3_HAS_SDRC;
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/*
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* TODO: Get additional info (where applicable)
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* e.g. Size of L2 cache.
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*/
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omap3_cpuinfo();
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}
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void __init omap4xxx_check_features(void)
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{
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u32 si_type;
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if (cpu_is_omap443x())
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omap_features |= OMAP4_HAS_MPU_1GHZ;
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if (cpu_is_omap446x()) {
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si_type =
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read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
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switch ((si_type & (3 << 16)) >> 16) {
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case 2:
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/* High performance device */
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omap_features |= OMAP4_HAS_MPU_1_5GHZ;
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break;
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case 1:
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default:
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/* Standard device */
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omap_features |= OMAP4_HAS_MPU_1_2GHZ;
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break;
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}
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}
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}
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void __init ti81xx_check_features(void)
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{
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omap_features = OMAP3_HAS_NEON;
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omap3_cpuinfo();
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}
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void __init omap3xxx_check_revision(void)
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{
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u32 cpuid, idcode;
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u16 hawkeye;
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u8 rev;
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/*
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* We cannot access revision registers on ES1.0.
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* If the processor type is Cortex-A8 and the revision is 0x0
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* it means its Cortex r0p0 which is 3430 ES1.0.
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*/
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cpuid = read_cpuid(CPUID_ID);
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if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
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omap_revision = OMAP3430_REV_ES1_0;
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cpu_rev = "1.0";
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return;
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}
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/*
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* Detection for 34xx ES2.0 and above can be done with just
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* hawkeye and rev. See TRM 1.5.2 Device Identification.
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* Note that rev does not map directly to our defined processor
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* revision numbers as ES1.0 uses value 0.
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*/
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idcode = read_tap_reg(OMAP_TAP_IDCODE);
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hawkeye = (idcode >> 12) & 0xffff;
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rev = (idcode >> 28) & 0xff;
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switch (hawkeye) {
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case 0xb7ae:
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/* Handle 34xx/35xx devices */
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switch (rev) {
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case 0: /* Take care of early samples */
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case 1:
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omap_revision = OMAP3430_REV_ES2_0;
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cpu_rev = "2.0";
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break;
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case 2:
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omap_revision = OMAP3430_REV_ES2_1;
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cpu_rev = "2.1";
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break;
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case 3:
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omap_revision = OMAP3430_REV_ES3_0;
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cpu_rev = "3.0";
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break;
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case 4:
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omap_revision = OMAP3430_REV_ES3_1;
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cpu_rev = "3.1";
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break;
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case 7:
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/* FALLTHROUGH */
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default:
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/* Use the latest known revision as default */
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omap_revision = OMAP3430_REV_ES3_1_2;
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cpu_rev = "3.1.2";
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}
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break;
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case 0xb868:
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/*
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* Handle OMAP/AM 3505/3517 devices
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*
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* Set the device to be OMAP3517 here. Actual device
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* is identified later based on the features.
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*/
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switch (rev) {
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case 0:
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omap_revision = OMAP3517_REV_ES1_0;
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cpu_rev = "1.0";
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break;
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case 1:
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/* FALLTHROUGH */
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default:
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omap_revision = OMAP3517_REV_ES1_1;
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cpu_rev = "1.1";
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}
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break;
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case 0xb891:
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/* Handle 36xx devices */
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switch(rev) {
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case 0: /* Take care of early samples */
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omap_revision = OMAP3630_REV_ES1_0;
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cpu_rev = "1.0";
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break;
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case 1:
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omap_revision = OMAP3630_REV_ES1_1;
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cpu_rev = "1.1";
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break;
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case 2:
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/* FALLTHROUGH */
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default:
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omap_revision = OMAP3630_REV_ES1_2;
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cpu_rev = "1.2";
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}
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break;
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case 0xb81e:
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switch (rev) {
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case 0:
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omap_revision = TI8168_REV_ES1_0;
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cpu_rev = "1.0";
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break;
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case 1:
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/* FALLTHROUGH */
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default:
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omap_revision = TI8168_REV_ES1_1;
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cpu_rev = "1.1";
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break;
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}
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break;
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case 0xb944:
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omap_revision = AM335X_REV_ES1_0;
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cpu_rev = "1.0";
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break;
|
|
case 0xb8f2:
|
|
switch (rev) {
|
|
case 0:
|
|
/* FALLTHROUGH */
|
|
case 1:
|
|
omap_revision = TI8148_REV_ES1_0;
|
|
cpu_rev = "1.0";
|
|
break;
|
|
case 2:
|
|
omap_revision = TI8148_REV_ES2_0;
|
|
cpu_rev = "2.0";
|
|
break;
|
|
case 3:
|
|
/* FALLTHROUGH */
|
|
default:
|
|
omap_revision = TI8148_REV_ES2_1;
|
|
cpu_rev = "2.1";
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
/* Unknown default to latest silicon rev as default */
|
|
omap_revision = OMAP3630_REV_ES1_2;
|
|
cpu_rev = "1.2";
|
|
pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
|
|
}
|
|
}
|
|
|
|
void __init omap4xxx_check_revision(void)
|
|
{
|
|
u32 idcode;
|
|
u16 hawkeye;
|
|
u8 rev;
|
|
|
|
/*
|
|
* The IC rev detection is done with hawkeye and rev.
|
|
* Note that rev does not map directly to defined processor
|
|
* revision numbers as ES1.0 uses value 0.
|
|
*/
|
|
idcode = read_tap_reg(OMAP_TAP_IDCODE);
|
|
hawkeye = (idcode >> 12) & 0xffff;
|
|
rev = (idcode >> 28) & 0xf;
|
|
|
|
/*
|
|
* Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
|
|
* Use ARM register to detect the correct ES version
|
|
*/
|
|
if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
|
|
idcode = read_cpuid(CPUID_ID);
|
|
rev = (idcode & 0xf) - 1;
|
|
}
|
|
|
|
switch (hawkeye) {
|
|
case 0xb852:
|
|
switch (rev) {
|
|
case 0:
|
|
omap_revision = OMAP4430_REV_ES1_0;
|
|
break;
|
|
case 1:
|
|
default:
|
|
omap_revision = OMAP4430_REV_ES2_0;
|
|
}
|
|
break;
|
|
case 0xb95c:
|
|
switch (rev) {
|
|
case 3:
|
|
omap_revision = OMAP4430_REV_ES2_1;
|
|
break;
|
|
case 4:
|
|
omap_revision = OMAP4430_REV_ES2_2;
|
|
break;
|
|
case 6:
|
|
default:
|
|
omap_revision = OMAP4430_REV_ES2_3;
|
|
}
|
|
break;
|
|
case 0xb94e:
|
|
switch (rev) {
|
|
case 0:
|
|
default:
|
|
omap_revision = OMAP4460_REV_ES1_0;
|
|
break;
|
|
}
|
|
break;
|
|
case 0xb975:
|
|
switch (rev) {
|
|
case 0:
|
|
default:
|
|
omap_revision = OMAP4470_REV_ES1_0;
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
/* Unknown default to latest silicon rev as default */
|
|
omap_revision = OMAP4430_REV_ES2_3;
|
|
}
|
|
|
|
pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
|
|
((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
|
|
}
|
|
|
|
/*
|
|
* Set up things for map_io and processor detection later on. Gets called
|
|
* pretty much first thing from board init. For multi-omap, this gets
|
|
* cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
|
|
* detect the exact revision later on in omap2_detect_revision() once map_io
|
|
* is done.
|
|
*/
|
|
void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
|
|
{
|
|
omap_revision = omap2_globals->class;
|
|
tap_base = omap2_globals->tap;
|
|
|
|
if (cpu_is_omap34xx())
|
|
tap_prod_id = 0x0210;
|
|
else
|
|
tap_prod_id = 0x0208;
|
|
}
|