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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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10d8935f46
viresh.kumar@st.com email-id doesn't exist anymore as I have left the company. Replace ST's id with viresh.linux@gmail.com. It also updates .mailmap file to fix address for 'git shortlog' Signed-off-by: Viresh Kumar <viresh.linux@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
155 lines
3.5 KiB
C
155 lines
3.5 KiB
C
/*
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* Copyright (C) 2012 ST Microelectronics
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* Viresh Kumar <viresh.linux@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* General Purpose Timer Synthesizer clock implementation
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*/
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#define pr_fmt(fmt) "clk-gpt-synth: " fmt
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include "clk.h"
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#define GPT_MSCALE_MASK 0xFFF
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#define GPT_NSCALE_SHIFT 12
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#define GPT_NSCALE_MASK 0xF
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/*
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* DOC: General Purpose Timer Synthesizer clock
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*
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* Calculates gpt synth clk rate for different values of mscale and nscale
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*
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* Fout= Fin/((2 ^ (N+1)) * (M+1))
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*/
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#define to_clk_gpt(_hw) container_of(_hw, struct clk_gpt, hw)
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static unsigned long gpt_calc_rate(struct clk_hw *hw, unsigned long prate,
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int index)
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{
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struct clk_gpt *gpt = to_clk_gpt(hw);
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struct gpt_rate_tbl *rtbl = gpt->rtbl;
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prate /= ((1 << (rtbl[index].nscale + 1)) * (rtbl[index].mscale + 1));
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return prate;
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}
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static long clk_gpt_round_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long *prate)
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{
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struct clk_gpt *gpt = to_clk_gpt(hw);
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int unused;
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return clk_round_rate_index(hw, drate, *prate, gpt_calc_rate,
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gpt->rtbl_cnt, &unused);
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}
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static unsigned long clk_gpt_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_gpt *gpt = to_clk_gpt(hw);
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unsigned long flags = 0;
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unsigned int div = 1, val;
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if (gpt->lock)
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spin_lock_irqsave(gpt->lock, flags);
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val = readl_relaxed(gpt->reg);
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if (gpt->lock)
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spin_unlock_irqrestore(gpt->lock, flags);
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div += val & GPT_MSCALE_MASK;
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div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1);
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if (!div)
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return 0;
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return parent_rate / div;
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}
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/* Configures new clock rate of gpt */
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static int clk_gpt_set_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long prate)
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{
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struct clk_gpt *gpt = to_clk_gpt(hw);
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struct gpt_rate_tbl *rtbl = gpt->rtbl;
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unsigned long flags = 0, val;
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int i;
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clk_round_rate_index(hw, drate, prate, gpt_calc_rate, gpt->rtbl_cnt,
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&i);
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if (gpt->lock)
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spin_lock_irqsave(gpt->lock, flags);
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val = readl(gpt->reg) & ~GPT_MSCALE_MASK;
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val &= ~(GPT_NSCALE_MASK << GPT_NSCALE_SHIFT);
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val |= rtbl[i].mscale & GPT_MSCALE_MASK;
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val |= (rtbl[i].nscale & GPT_NSCALE_MASK) << GPT_NSCALE_SHIFT;
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writel_relaxed(val, gpt->reg);
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if (gpt->lock)
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spin_unlock_irqrestore(gpt->lock, flags);
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return 0;
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}
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static struct clk_ops clk_gpt_ops = {
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.recalc_rate = clk_gpt_recalc_rate,
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.round_rate = clk_gpt_round_rate,
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.set_rate = clk_gpt_set_rate,
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};
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struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
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long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8
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rtbl_cnt, spinlock_t *lock)
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{
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struct clk_init_data init;
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struct clk_gpt *gpt;
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struct clk *clk;
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if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
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pr_err("Invalid arguments passed");
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return ERR_PTR(-EINVAL);
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}
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gpt = kzalloc(sizeof(*gpt), GFP_KERNEL);
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if (!gpt) {
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pr_err("could not allocate gpt clk\n");
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return ERR_PTR(-ENOMEM);
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}
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/* struct clk_gpt assignments */
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gpt->reg = reg;
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gpt->rtbl = rtbl;
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gpt->rtbl_cnt = rtbl_cnt;
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gpt->lock = lock;
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gpt->hw.init = &init;
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init.name = name;
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init.ops = &clk_gpt_ops;
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init.flags = flags;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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clk = clk_register(NULL, &gpt->hw);
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if (!IS_ERR_OR_NULL(clk))
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return clk;
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pr_err("clk register failed\n");
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kfree(gpt);
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return NULL;
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}
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