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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f00ec48fad
UP systems do not implement all the instructions that SMP systems have, so in order to boot a SMP kernel on a UP system, we need to rewrite parts of the kernel. Do this using an 'alternatives' scheme, where the kernel code and data is modified prior to initialization to replace the SMP instructions, thereby rendering the problematical code ineffectual. We use the linker to generate a list of 32-bit word locations and their replacement values, and run through these replacements when we detect a UP system. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1248 lines
29 KiB
ArmAsm
1248 lines
29 KiB
ArmAsm
/*
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* linux/arch/arm/kernel/entry-armv.S
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*
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* Copyright (C) 1996,1997,1998 Russell King.
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* ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
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* nommu support by Hyok S. Choi (hyok.choi@samsung.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Low-level vector interface routines
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*
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* Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
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* that causes it to save wrong values... Be aware!
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*/
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#include <asm/memory.h>
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#include <asm/glue.h>
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#include <asm/vfpmacros.h>
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#include <mach/entry-macro.S>
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#include <asm/thread_notify.h>
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#include <asm/unwind.h>
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#include <asm/unistd.h>
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#include <asm/tls.h>
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#include "entry-header.S"
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/*
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* Interrupt handling. Preserves r7, r8, r9
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*/
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.macro irq_handler
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get_irqnr_preamble r5, lr
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1: get_irqnr_and_base r0, r6, r5, lr
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movne r1, sp
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@
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@ routine called with r0 = irq number, r1 = struct pt_regs *
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@
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adrne lr, BSYM(1b)
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bne asm_do_IRQ
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#ifdef CONFIG_SMP
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/*
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* XXX
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*
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* this macro assumes that irqstat (r6) and base (r5) are
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* preserved from get_irqnr_and_base above
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*/
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ALT_SMP(test_for_ipi r0, r6, r5, lr)
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ALT_UP_B(9997f)
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movne r0, sp
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adrne lr, BSYM(1b)
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bne do_IPI
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#ifdef CONFIG_LOCAL_TIMERS
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test_for_ltirq r0, r6, r5, lr
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movne r0, sp
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adrne lr, BSYM(1b)
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bne do_local_timer
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#endif
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9997:
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#endif
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.endm
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#ifdef CONFIG_KPROBES
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.section .kprobes.text,"ax",%progbits
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#else
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.text
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#endif
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/*
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* Invalid mode handlers
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*/
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.macro inv_entry, reason
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sub sp, sp, #S_FRAME_SIZE
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ARM( stmib sp, {r1 - lr} )
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THUMB( stmia sp, {r0 - r12} )
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THUMB( str sp, [sp, #S_SP] )
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THUMB( str lr, [sp, #S_LR] )
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mov r1, #\reason
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.endm
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__pabt_invalid:
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inv_entry BAD_PREFETCH
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b common_invalid
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ENDPROC(__pabt_invalid)
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__dabt_invalid:
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inv_entry BAD_DATA
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b common_invalid
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ENDPROC(__dabt_invalid)
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__irq_invalid:
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inv_entry BAD_IRQ
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b common_invalid
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ENDPROC(__irq_invalid)
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__und_invalid:
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inv_entry BAD_UNDEFINSTR
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@
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@ XXX fall through to common_invalid
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@
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@
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@ common_invalid - generic code for failed exception (re-entrant version of handlers)
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@
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common_invalid:
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zero_fp
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ldmia r0, {r4 - r6}
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add r0, sp, #S_PC @ here for interlock avoidance
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mov r7, #-1 @ "" "" "" ""
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str r4, [sp] @ save preserved r0
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stmia r0, {r5 - r7} @ lr_<exception>,
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@ cpsr_<exception>, "old_r0"
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mov r0, sp
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b bad_mode
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ENDPROC(__und_invalid)
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/*
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* SVC mode handlers
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*/
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#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
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#define SPFIX(code...) code
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#else
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#define SPFIX(code...)
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#endif
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.macro svc_entry, stack_hole=0
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UNWIND(.fnstart )
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UNWIND(.save {r0 - pc} )
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sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
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#ifdef CONFIG_THUMB2_KERNEL
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SPFIX( str r0, [sp] ) @ temporarily saved
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SPFIX( mov r0, sp )
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SPFIX( tst r0, #4 ) @ test original stack alignment
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SPFIX( ldr r0, [sp] ) @ restored
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#else
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SPFIX( tst sp, #4 )
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#endif
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SPFIX( subeq sp, sp, #4 )
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stmia sp, {r1 - r12}
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ldmia r0, {r1 - r3}
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add r5, sp, #S_SP - 4 @ here for interlock avoidance
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mov r4, #-1 @ "" "" "" ""
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add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
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SPFIX( addeq r0, r0, #4 )
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str r1, [sp, #-4]! @ save the "real" r0 copied
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@ from the exception stack
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mov r1, lr
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@
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@ We are now ready to fill in the remaining blanks on the stack:
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@
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@ r0 - sp_svc
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@ r1 - lr_svc
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@ r2 - lr_<exception>, already fixed up for correct return/restart
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@ r3 - spsr_<exception>
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@ r4 - orig_r0 (see pt_regs definition in ptrace.h)
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@
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stmia r5, {r0 - r4}
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.endm
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.align 5
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__dabt_svc:
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svc_entry
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@
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@ get ready to re-enable interrupts if appropriate
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@
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mrs r9, cpsr
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tst r3, #PSR_I_BIT
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biceq r9, r9, #PSR_I_BIT
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@
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@ Call the processor-specific abort handler:
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@
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@ r2 - aborted context pc
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@ r3 - aborted context cpsr
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@
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@ The abort handler must return the aborted address in r0, and
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@ the fault status register in r1. r9 must be preserved.
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@
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#ifdef MULTI_DABORT
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ldr r4, .LCprocfns
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mov lr, pc
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ldr pc, [r4, #PROCESSOR_DABT_FUNC]
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#else
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bl CPU_DABORT_HANDLER
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#endif
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@
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@ set desired IRQ state, then call main handler
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@
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msr cpsr_c, r9
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mov r2, sp
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bl do_DataAbort
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@
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@ IRQs off again before pulling preserved data off the stack
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@
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disable_irq_notrace
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@
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@ restore SPSR and restart the instruction
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@
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ldr r2, [sp, #S_PSR]
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svc_exit r2 @ return from exception
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UNWIND(.fnend )
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ENDPROC(__dabt_svc)
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.align 5
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__irq_svc:
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svc_entry
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl trace_hardirqs_off
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#endif
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#ifdef CONFIG_PREEMPT
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get_thread_info tsk
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ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
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add r7, r8, #1 @ increment it
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str r7, [tsk, #TI_PREEMPT]
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#endif
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irq_handler
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#ifdef CONFIG_PREEMPT
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str r8, [tsk, #TI_PREEMPT] @ restore preempt count
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ldr r0, [tsk, #TI_FLAGS] @ get flags
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teq r8, #0 @ if preempt count != 0
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movne r0, #0 @ force flags to 0
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tst r0, #_TIF_NEED_RESCHED
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blne svc_preempt
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#endif
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ldr r4, [sp, #S_PSR] @ irqs are already disabled
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#ifdef CONFIG_TRACE_IRQFLAGS
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tst r4, #PSR_I_BIT
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bleq trace_hardirqs_on
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#endif
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svc_exit r4 @ return from exception
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UNWIND(.fnend )
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ENDPROC(__irq_svc)
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.ltorg
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#ifdef CONFIG_PREEMPT
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svc_preempt:
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mov r8, lr
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1: bl preempt_schedule_irq @ irq en/disable is done inside
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ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
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tst r0, #_TIF_NEED_RESCHED
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moveq pc, r8 @ go again
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b 1b
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#endif
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.align 5
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__und_svc:
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#ifdef CONFIG_KPROBES
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@ If a kprobe is about to simulate a "stmdb sp..." instruction,
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@ it obviously needs free stack space which then will belong to
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@ the saved context.
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svc_entry 64
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#else
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svc_entry
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#endif
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@
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@ call emulation code, which returns using r9 if it has emulated
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@ the instruction, or the more conventional lr if we are to treat
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@ this as a real undefined instruction
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@
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@ r0 - instruction
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@
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#ifndef CONFIG_THUMB2_KERNEL
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ldr r0, [r2, #-4]
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#else
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ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
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and r9, r0, #0xf800
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cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
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ldrhhs r9, [r2] @ bottom 16 bits
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orrhs r0, r9, r0, lsl #16
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#endif
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adr r9, BSYM(1f)
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bl call_fpe
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mov r0, sp @ struct pt_regs *regs
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bl do_undefinstr
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@
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@ IRQs off again before pulling preserved data off the stack
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@
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1: disable_irq_notrace
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@
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@ restore SPSR and restart the instruction
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@
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ldr r2, [sp, #S_PSR] @ Get SVC cpsr
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svc_exit r2 @ return from exception
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UNWIND(.fnend )
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ENDPROC(__und_svc)
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.align 5
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__pabt_svc:
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svc_entry
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@
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@ re-enable interrupts if appropriate
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@
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mrs r9, cpsr
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tst r3, #PSR_I_BIT
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biceq r9, r9, #PSR_I_BIT
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mov r0, r2 @ pass address of aborted instruction.
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#ifdef MULTI_PABORT
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ldr r4, .LCprocfns
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mov lr, pc
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ldr pc, [r4, #PROCESSOR_PABT_FUNC]
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#else
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bl CPU_PABORT_HANDLER
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#endif
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msr cpsr_c, r9 @ Maybe enable interrupts
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mov r2, sp @ regs
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bl do_PrefetchAbort @ call abort handler
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@
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@ IRQs off again before pulling preserved data off the stack
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@
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disable_irq_notrace
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@
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@ restore SPSR and restart the instruction
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@
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ldr r2, [sp, #S_PSR]
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svc_exit r2 @ return from exception
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UNWIND(.fnend )
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ENDPROC(__pabt_svc)
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.align 5
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.LCcralign:
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.word cr_alignment
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#ifdef MULTI_DABORT
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.LCprocfns:
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.word processor
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#endif
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.LCfp:
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.word fp_enter
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/*
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* User mode handlers
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*
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* EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
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*/
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#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
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#error "sizeof(struct pt_regs) must be a multiple of 8"
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#endif
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.macro usr_entry
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UNWIND(.fnstart )
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UNWIND(.cantunwind ) @ don't unwind the user space
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sub sp, sp, #S_FRAME_SIZE
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ARM( stmib sp, {r1 - r12} )
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THUMB( stmia sp, {r0 - r12} )
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ldmia r0, {r1 - r3}
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add r0, sp, #S_PC @ here for interlock avoidance
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mov r4, #-1 @ "" "" "" ""
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str r1, [sp] @ save the "real" r0 copied
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@ from the exception stack
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@
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@ We are now ready to fill in the remaining blanks on the stack:
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@
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@ r2 - lr_<exception>, already fixed up for correct return/restart
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@ r3 - spsr_<exception>
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@ r4 - orig_r0 (see pt_regs definition in ptrace.h)
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@
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@ Also, separately save sp_usr and lr_usr
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@
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stmia r0, {r2 - r4}
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ARM( stmdb r0, {sp, lr}^ )
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THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
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@
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@ Enable the alignment trap while in kernel mode
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@
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alignment_trap r0
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@
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@ Clear FP to mark the first stack frame
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@
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zero_fp
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.endm
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.macro kuser_cmpxchg_check
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#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
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#ifndef CONFIG_MMU
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#warning "NPTL on non MMU needs fixing"
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#else
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@ Make sure our user space atomic helper is restarted
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@ if it was interrupted in a critical region. Here we
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@ perform a quick test inline since it should be false
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@ 99.9999% of the time. The rest is done out of line.
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cmp r2, #TASK_SIZE
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blhs kuser_cmpxchg_fixup
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#endif
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#endif
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.endm
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.align 5
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__dabt_usr:
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usr_entry
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kuser_cmpxchg_check
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@
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@ Call the processor-specific abort handler:
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@
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@ r2 - aborted context pc
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@ r3 - aborted context cpsr
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@
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@ The abort handler must return the aborted address in r0, and
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@ the fault status register in r1.
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@
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#ifdef MULTI_DABORT
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ldr r4, .LCprocfns
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mov lr, pc
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ldr pc, [r4, #PROCESSOR_DABT_FUNC]
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#else
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bl CPU_DABORT_HANDLER
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#endif
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@
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@ IRQs on, then call the main handler
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@
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enable_irq
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mov r2, sp
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adr lr, BSYM(ret_from_exception)
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b do_DataAbort
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UNWIND(.fnend )
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ENDPROC(__dabt_usr)
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.align 5
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__irq_usr:
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usr_entry
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kuser_cmpxchg_check
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get_thread_info tsk
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#ifdef CONFIG_PREEMPT
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ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
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add r7, r8, #1 @ increment it
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str r7, [tsk, #TI_PREEMPT]
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#endif
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irq_handler
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#ifdef CONFIG_PREEMPT
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ldr r0, [tsk, #TI_PREEMPT]
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str r8, [tsk, #TI_PREEMPT]
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teq r0, r7
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ARM( strne r0, [r0, -r0] )
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THUMB( movne r0, #0 )
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THUMB( strne r0, [r0] )
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#endif
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mov why, #0
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b ret_to_user
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UNWIND(.fnend )
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ENDPROC(__irq_usr)
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.ltorg
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.align 5
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__und_usr:
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usr_entry
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@
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@ fall through to the emulation code, which returns using r9 if
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@ it has emulated the instruction, or the more conventional lr
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@ if we are to treat this as a real undefined instruction
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@
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@ r0 - instruction
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@
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adr r9, BSYM(ret_from_exception)
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adr lr, BSYM(__und_usr_unknown)
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tst r3, #PSR_T_BIT @ Thumb mode?
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itet eq @ explicit IT needed for the 1f label
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subeq r4, r2, #4 @ ARM instr at LR - 4
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subne r4, r2, #2 @ Thumb instr at LR - 2
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1: ldreqt r0, [r4]
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#ifdef CONFIG_CPU_ENDIAN_BE8
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reveq r0, r0 @ little endian instruction
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#endif
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beq call_fpe
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@ Thumb instruction
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#if __LINUX_ARM_ARCH__ >= 7
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2:
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ARM( ldrht r5, [r4], #2 )
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THUMB( ldrht r5, [r4] )
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THUMB( add r4, r4, #2 )
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and r0, r5, #0xf800 @ mask bits 111x x... .... ....
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cmp r0, #0xe800 @ 32bit instruction if xx != 0
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blo __und_usr_unknown
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3: ldrht r0, [r4]
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add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
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orr r0, r0, r5, lsl #16
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#else
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b __und_usr_unknown
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#endif
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UNWIND(.fnend )
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ENDPROC(__und_usr)
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@
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@ fallthrough to call_fpe
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@
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/*
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* The out of line fixup for the ldrt above.
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*/
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.pushsection .fixup, "ax"
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4: mov pc, r9
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.popsection
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.pushsection __ex_table,"a"
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.long 1b, 4b
|
|
#if __LINUX_ARM_ARCH__ >= 7
|
|
.long 2b, 4b
|
|
.long 3b, 4b
|
|
#endif
|
|
.popsection
|
|
|
|
/*
|
|
* Check whether the instruction is a co-processor instruction.
|
|
* If yes, we need to call the relevant co-processor handler.
|
|
*
|
|
* Note that we don't do a full check here for the co-processor
|
|
* instructions; all instructions with bit 27 set are well
|
|
* defined. The only instructions that should fault are the
|
|
* co-processor instructions. However, we have to watch out
|
|
* for the ARM6/ARM7 SWI bug.
|
|
*
|
|
* NEON is a special case that has to be handled here. Not all
|
|
* NEON instructions are co-processor instructions, so we have
|
|
* to make a special case of checking for them. Plus, there's
|
|
* five groups of them, so we have a table of mask/opcode pairs
|
|
* to check against, and if any match then we branch off into the
|
|
* NEON handler code.
|
|
*
|
|
* Emulators may wish to make use of the following registers:
|
|
* r0 = instruction opcode.
|
|
* r2 = PC+4
|
|
* r9 = normal "successful" return address
|
|
* r10 = this threads thread_info structure.
|
|
* lr = unrecognised instruction return address
|
|
*/
|
|
@
|
|
@ Fall-through from Thumb-2 __und_usr
|
|
@
|
|
#ifdef CONFIG_NEON
|
|
adr r6, .LCneon_thumb_opcodes
|
|
b 2f
|
|
#endif
|
|
call_fpe:
|
|
#ifdef CONFIG_NEON
|
|
adr r6, .LCneon_arm_opcodes
|
|
2:
|
|
ldr r7, [r6], #4 @ mask value
|
|
cmp r7, #0 @ end mask?
|
|
beq 1f
|
|
and r8, r0, r7
|
|
ldr r7, [r6], #4 @ opcode bits matching in mask
|
|
cmp r8, r7 @ NEON instruction?
|
|
bne 2b
|
|
get_thread_info r10
|
|
mov r7, #1
|
|
strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
|
|
strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
|
|
b do_vfp @ let VFP handler handle this
|
|
1:
|
|
#endif
|
|
tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
|
|
tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
|
|
#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
|
|
and r8, r0, #0x0f000000 @ mask out op-code bits
|
|
teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
|
|
#endif
|
|
moveq pc, lr
|
|
get_thread_info r10 @ get current thread
|
|
and r8, r0, #0x00000f00 @ mask out CP number
|
|
THUMB( lsr r8, r8, #8 )
|
|
mov r7, #1
|
|
add r6, r10, #TI_USED_CP
|
|
ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
|
|
THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
|
|
#ifdef CONFIG_IWMMXT
|
|
@ Test if we need to give access to iWMMXt coprocessors
|
|
ldr r5, [r10, #TI_FLAGS]
|
|
rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
|
|
movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
|
|
bcs iwmmxt_task_enable
|
|
#endif
|
|
ARM( add pc, pc, r8, lsr #6 )
|
|
THUMB( lsl r8, r8, #2 )
|
|
THUMB( add pc, r8 )
|
|
nop
|
|
|
|
movw_pc lr @ CP#0
|
|
W(b) do_fpe @ CP#1 (FPE)
|
|
W(b) do_fpe @ CP#2 (FPE)
|
|
movw_pc lr @ CP#3
|
|
#ifdef CONFIG_CRUNCH
|
|
b crunch_task_enable @ CP#4 (MaverickCrunch)
|
|
b crunch_task_enable @ CP#5 (MaverickCrunch)
|
|
b crunch_task_enable @ CP#6 (MaverickCrunch)
|
|
#else
|
|
movw_pc lr @ CP#4
|
|
movw_pc lr @ CP#5
|
|
movw_pc lr @ CP#6
|
|
#endif
|
|
movw_pc lr @ CP#7
|
|
movw_pc lr @ CP#8
|
|
movw_pc lr @ CP#9
|
|
#ifdef CONFIG_VFP
|
|
W(b) do_vfp @ CP#10 (VFP)
|
|
W(b) do_vfp @ CP#11 (VFP)
|
|
#else
|
|
movw_pc lr @ CP#10 (VFP)
|
|
movw_pc lr @ CP#11 (VFP)
|
|
#endif
|
|
movw_pc lr @ CP#12
|
|
movw_pc lr @ CP#13
|
|
movw_pc lr @ CP#14 (Debug)
|
|
movw_pc lr @ CP#15 (Control)
|
|
|
|
#ifdef CONFIG_NEON
|
|
.align 6
|
|
|
|
.LCneon_arm_opcodes:
|
|
.word 0xfe000000 @ mask
|
|
.word 0xf2000000 @ opcode
|
|
|
|
.word 0xff100000 @ mask
|
|
.word 0xf4000000 @ opcode
|
|
|
|
.word 0x00000000 @ mask
|
|
.word 0x00000000 @ opcode
|
|
|
|
.LCneon_thumb_opcodes:
|
|
.word 0xef000000 @ mask
|
|
.word 0xef000000 @ opcode
|
|
|
|
.word 0xff100000 @ mask
|
|
.word 0xf9000000 @ opcode
|
|
|
|
.word 0x00000000 @ mask
|
|
.word 0x00000000 @ opcode
|
|
#endif
|
|
|
|
do_fpe:
|
|
enable_irq
|
|
ldr r4, .LCfp
|
|
add r10, r10, #TI_FPSTATE @ r10 = workspace
|
|
ldr pc, [r4] @ Call FP module USR entry point
|
|
|
|
/*
|
|
* The FP module is called with these registers set:
|
|
* r0 = instruction
|
|
* r2 = PC+4
|
|
* r9 = normal "successful" return address
|
|
* r10 = FP workspace
|
|
* lr = unrecognised FP instruction return address
|
|
*/
|
|
|
|
.pushsection .data
|
|
ENTRY(fp_enter)
|
|
.word no_fp
|
|
.popsection
|
|
|
|
ENTRY(no_fp)
|
|
mov pc, lr
|
|
ENDPROC(no_fp)
|
|
|
|
__und_usr_unknown:
|
|
enable_irq
|
|
mov r0, sp
|
|
adr lr, BSYM(ret_from_exception)
|
|
b do_undefinstr
|
|
ENDPROC(__und_usr_unknown)
|
|
|
|
.align 5
|
|
__pabt_usr:
|
|
usr_entry
|
|
|
|
mov r0, r2 @ pass address of aborted instruction.
|
|
#ifdef MULTI_PABORT
|
|
ldr r4, .LCprocfns
|
|
mov lr, pc
|
|
ldr pc, [r4, #PROCESSOR_PABT_FUNC]
|
|
#else
|
|
bl CPU_PABORT_HANDLER
|
|
#endif
|
|
enable_irq @ Enable interrupts
|
|
mov r2, sp @ regs
|
|
bl do_PrefetchAbort @ call abort handler
|
|
UNWIND(.fnend )
|
|
/* fall through */
|
|
/*
|
|
* This is the return code to user mode for abort handlers
|
|
*/
|
|
ENTRY(ret_from_exception)
|
|
UNWIND(.fnstart )
|
|
UNWIND(.cantunwind )
|
|
get_thread_info tsk
|
|
mov why, #0
|
|
b ret_to_user
|
|
UNWIND(.fnend )
|
|
ENDPROC(__pabt_usr)
|
|
ENDPROC(ret_from_exception)
|
|
|
|
/*
|
|
* Register switch for ARMv3 and ARMv4 processors
|
|
* r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
|
|
* previous and next are guaranteed not to be the same.
|
|
*/
|
|
ENTRY(__switch_to)
|
|
UNWIND(.fnstart )
|
|
UNWIND(.cantunwind )
|
|
add ip, r1, #TI_CPU_SAVE
|
|
ldr r3, [r2, #TI_TP_VALUE]
|
|
ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
|
|
THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
|
|
THUMB( str sp, [ip], #4 )
|
|
THUMB( str lr, [ip], #4 )
|
|
#ifdef CONFIG_MMU
|
|
ldr r6, [r2, #TI_CPU_DOMAIN]
|
|
#endif
|
|
set_tls r3, r4, r5
|
|
#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
|
|
ldr r7, [r2, #TI_TASK]
|
|
ldr r8, =__stack_chk_guard
|
|
ldr r7, [r7, #TSK_STACK_CANARY]
|
|
#endif
|
|
#ifdef CONFIG_MMU
|
|
mcr p15, 0, r6, c3, c0, 0 @ Set domain register
|
|
#endif
|
|
mov r5, r0
|
|
add r4, r2, #TI_CPU_SAVE
|
|
ldr r0, =thread_notify_head
|
|
mov r1, #THREAD_NOTIFY_SWITCH
|
|
bl atomic_notifier_call_chain
|
|
#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
|
|
str r7, [r8]
|
|
#endif
|
|
THUMB( mov ip, r4 )
|
|
mov r0, r5
|
|
ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
|
|
THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
|
|
THUMB( ldr sp, [ip], #4 )
|
|
THUMB( ldr pc, [ip] )
|
|
UNWIND(.fnend )
|
|
ENDPROC(__switch_to)
|
|
|
|
__INIT
|
|
|
|
/*
|
|
* User helpers.
|
|
*
|
|
* These are segment of kernel provided user code reachable from user space
|
|
* at a fixed address in kernel memory. This is used to provide user space
|
|
* with some operations which require kernel help because of unimplemented
|
|
* native feature and/or instructions in many ARM CPUs. The idea is for
|
|
* this code to be executed directly in user mode for best efficiency but
|
|
* which is too intimate with the kernel counter part to be left to user
|
|
* libraries. In fact this code might even differ from one CPU to another
|
|
* depending on the available instruction set and restrictions like on
|
|
* SMP systems. In other words, the kernel reserves the right to change
|
|
* this code as needed without warning. Only the entry points and their
|
|
* results are guaranteed to be stable.
|
|
*
|
|
* Each segment is 32-byte aligned and will be moved to the top of the high
|
|
* vector page. New segments (if ever needed) must be added in front of
|
|
* existing ones. This mechanism should be used only for things that are
|
|
* really small and justified, and not be abused freely.
|
|
*
|
|
* User space is expected to implement those things inline when optimizing
|
|
* for a processor that has the necessary native support, but only if such
|
|
* resulting binaries are already to be incompatible with earlier ARM
|
|
* processors due to the use of unsupported instructions other than what
|
|
* is provided here. In other words don't make binaries unable to run on
|
|
* earlier processors just for the sake of not using these kernel helpers
|
|
* if your compiled code is not going to use the new instructions for other
|
|
* purpose.
|
|
*/
|
|
THUMB( .arm )
|
|
|
|
.macro usr_ret, reg
|
|
#ifdef CONFIG_ARM_THUMB
|
|
bx \reg
|
|
#else
|
|
mov pc, \reg
|
|
#endif
|
|
.endm
|
|
|
|
.align 5
|
|
.globl __kuser_helper_start
|
|
__kuser_helper_start:
|
|
|
|
/*
|
|
* Reference prototype:
|
|
*
|
|
* void __kernel_memory_barrier(void)
|
|
*
|
|
* Input:
|
|
*
|
|
* lr = return address
|
|
*
|
|
* Output:
|
|
*
|
|
* none
|
|
*
|
|
* Clobbered:
|
|
*
|
|
* none
|
|
*
|
|
* Definition and user space usage example:
|
|
*
|
|
* typedef void (__kernel_dmb_t)(void);
|
|
* #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
|
|
*
|
|
* Apply any needed memory barrier to preserve consistency with data modified
|
|
* manually and __kuser_cmpxchg usage.
|
|
*
|
|
* This could be used as follows:
|
|
*
|
|
* #define __kernel_dmb() \
|
|
* asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
|
|
* : : : "r0", "lr","cc" )
|
|
*/
|
|
|
|
__kuser_memory_barrier: @ 0xffff0fa0
|
|
smp_dmb
|
|
usr_ret lr
|
|
|
|
.align 5
|
|
|
|
/*
|
|
* Reference prototype:
|
|
*
|
|
* int __kernel_cmpxchg(int oldval, int newval, int *ptr)
|
|
*
|
|
* Input:
|
|
*
|
|
* r0 = oldval
|
|
* r1 = newval
|
|
* r2 = ptr
|
|
* lr = return address
|
|
*
|
|
* Output:
|
|
*
|
|
* r0 = returned value (zero or non-zero)
|
|
* C flag = set if r0 == 0, clear if r0 != 0
|
|
*
|
|
* Clobbered:
|
|
*
|
|
* r3, ip, flags
|
|
*
|
|
* Definition and user space usage example:
|
|
*
|
|
* typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
|
|
* #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
|
|
*
|
|
* Atomically store newval in *ptr if *ptr is equal to oldval for user space.
|
|
* Return zero if *ptr was changed or non-zero if no exchange happened.
|
|
* The C flag is also set if *ptr was changed to allow for assembly
|
|
* optimization in the calling code.
|
|
*
|
|
* Notes:
|
|
*
|
|
* - This routine already includes memory barriers as needed.
|
|
*
|
|
* For example, a user space atomic_add implementation could look like this:
|
|
*
|
|
* #define atomic_add(ptr, val) \
|
|
* ({ register unsigned int *__ptr asm("r2") = (ptr); \
|
|
* register unsigned int __result asm("r1"); \
|
|
* asm volatile ( \
|
|
* "1: @ atomic_add\n\t" \
|
|
* "ldr r0, [r2]\n\t" \
|
|
* "mov r3, #0xffff0fff\n\t" \
|
|
* "add lr, pc, #4\n\t" \
|
|
* "add r1, r0, %2\n\t" \
|
|
* "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
|
|
* "bcc 1b" \
|
|
* : "=&r" (__result) \
|
|
* : "r" (__ptr), "rIL" (val) \
|
|
* : "r0","r3","ip","lr","cc","memory" ); \
|
|
* __result; })
|
|
*/
|
|
|
|
__kuser_cmpxchg: @ 0xffff0fc0
|
|
|
|
#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
|
|
|
|
/*
|
|
* Poor you. No fast solution possible...
|
|
* The kernel itself must perform the operation.
|
|
* A special ghost syscall is used for that (see traps.c).
|
|
*/
|
|
stmfd sp!, {r7, lr}
|
|
ldr r7, =1f @ it's 20 bits
|
|
swi __ARM_NR_cmpxchg
|
|
ldmfd sp!, {r7, pc}
|
|
1: .word __ARM_NR_cmpxchg
|
|
|
|
#elif __LINUX_ARM_ARCH__ < 6
|
|
|
|
#ifdef CONFIG_MMU
|
|
|
|
/*
|
|
* The only thing that can break atomicity in this cmpxchg
|
|
* implementation is either an IRQ or a data abort exception
|
|
* causing another process/thread to be scheduled in the middle
|
|
* of the critical sequence. To prevent this, code is added to
|
|
* the IRQ and data abort exception handlers to set the pc back
|
|
* to the beginning of the critical section if it is found to be
|
|
* within that critical section (see kuser_cmpxchg_fixup).
|
|
*/
|
|
1: ldr r3, [r2] @ load current val
|
|
subs r3, r3, r0 @ compare with oldval
|
|
2: streq r1, [r2] @ store newval if eq
|
|
rsbs r0, r3, #0 @ set return val and C flag
|
|
usr_ret lr
|
|
|
|
.text
|
|
kuser_cmpxchg_fixup:
|
|
@ Called from kuser_cmpxchg_check macro.
|
|
@ r2 = address of interrupted insn (must be preserved).
|
|
@ sp = saved regs. r7 and r8 are clobbered.
|
|
@ 1b = first critical insn, 2b = last critical insn.
|
|
@ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
|
|
mov r7, #0xffff0fff
|
|
sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
|
|
subs r8, r2, r7
|
|
rsbcss r8, r8, #(2b - 1b)
|
|
strcs r7, [sp, #S_PC]
|
|
mov pc, lr
|
|
.previous
|
|
|
|
#else
|
|
#warning "NPTL on non MMU needs fixing"
|
|
mov r0, #-1
|
|
adds r0, r0, #0
|
|
usr_ret lr
|
|
#endif
|
|
|
|
#else
|
|
|
|
smp_dmb
|
|
1: ldrex r3, [r2]
|
|
subs r3, r3, r0
|
|
strexeq r3, r1, [r2]
|
|
teqeq r3, #1
|
|
beq 1b
|
|
rsbs r0, r3, #0
|
|
/* beware -- each __kuser slot must be 8 instructions max */
|
|
ALT_SMP(b __kuser_memory_barrier)
|
|
ALT_UP(usr_ret lr)
|
|
|
|
#endif
|
|
|
|
.align 5
|
|
|
|
/*
|
|
* Reference prototype:
|
|
*
|
|
* int __kernel_get_tls(void)
|
|
*
|
|
* Input:
|
|
*
|
|
* lr = return address
|
|
*
|
|
* Output:
|
|
*
|
|
* r0 = TLS value
|
|
*
|
|
* Clobbered:
|
|
*
|
|
* none
|
|
*
|
|
* Definition and user space usage example:
|
|
*
|
|
* typedef int (__kernel_get_tls_t)(void);
|
|
* #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
|
|
*
|
|
* Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
|
|
*
|
|
* This could be used as follows:
|
|
*
|
|
* #define __kernel_get_tls() \
|
|
* ({ register unsigned int __val asm("r0"); \
|
|
* asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
|
|
* : "=r" (__val) : : "lr","cc" ); \
|
|
* __val; })
|
|
*/
|
|
|
|
__kuser_get_tls: @ 0xffff0fe0
|
|
ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
|
|
usr_ret lr
|
|
mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
|
|
.rep 4
|
|
.word 0 @ 0xffff0ff0 software TLS value, then
|
|
.endr @ pad up to __kuser_helper_version
|
|
|
|
/*
|
|
* Reference declaration:
|
|
*
|
|
* extern unsigned int __kernel_helper_version;
|
|
*
|
|
* Definition and user space usage example:
|
|
*
|
|
* #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
|
|
*
|
|
* User space may read this to determine the curent number of helpers
|
|
* available.
|
|
*/
|
|
|
|
__kuser_helper_version: @ 0xffff0ffc
|
|
.word ((__kuser_helper_end - __kuser_helper_start) >> 5)
|
|
|
|
.globl __kuser_helper_end
|
|
__kuser_helper_end:
|
|
|
|
THUMB( .thumb )
|
|
|
|
/*
|
|
* Vector stubs.
|
|
*
|
|
* This code is copied to 0xffff0200 so we can use branches in the
|
|
* vectors, rather than ldr's. Note that this code must not
|
|
* exceed 0x300 bytes.
|
|
*
|
|
* Common stub entry macro:
|
|
* Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
|
|
*
|
|
* SP points to a minimal amount of processor-private memory, the address
|
|
* of which is copied into r0 for the mode specific abort handler.
|
|
*/
|
|
.macro vector_stub, name, mode, correction=0
|
|
.align 5
|
|
|
|
vector_\name:
|
|
.if \correction
|
|
sub lr, lr, #\correction
|
|
.endif
|
|
|
|
@
|
|
@ Save r0, lr_<exception> (parent PC) and spsr_<exception>
|
|
@ (parent CPSR)
|
|
@
|
|
stmia sp, {r0, lr} @ save r0, lr
|
|
mrs lr, spsr
|
|
str lr, [sp, #8] @ save spsr
|
|
|
|
@
|
|
@ Prepare for SVC32 mode. IRQs remain disabled.
|
|
@
|
|
mrs r0, cpsr
|
|
eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
|
|
msr spsr_cxsf, r0
|
|
|
|
@
|
|
@ the branch table must immediately follow this code
|
|
@
|
|
and lr, lr, #0x0f
|
|
THUMB( adr r0, 1f )
|
|
THUMB( ldr lr, [r0, lr, lsl #2] )
|
|
mov r0, sp
|
|
ARM( ldr lr, [pc, lr, lsl #2] )
|
|
movs pc, lr @ branch to handler in SVC mode
|
|
ENDPROC(vector_\name)
|
|
|
|
.align 2
|
|
@ handler addresses follow this label
|
|
1:
|
|
.endm
|
|
|
|
.globl __stubs_start
|
|
__stubs_start:
|
|
/*
|
|
* Interrupt dispatcher
|
|
*/
|
|
vector_stub irq, IRQ_MODE, 4
|
|
|
|
.long __irq_usr @ 0 (USR_26 / USR_32)
|
|
.long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
|
|
.long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
|
|
.long __irq_svc @ 3 (SVC_26 / SVC_32)
|
|
.long __irq_invalid @ 4
|
|
.long __irq_invalid @ 5
|
|
.long __irq_invalid @ 6
|
|
.long __irq_invalid @ 7
|
|
.long __irq_invalid @ 8
|
|
.long __irq_invalid @ 9
|
|
.long __irq_invalid @ a
|
|
.long __irq_invalid @ b
|
|
.long __irq_invalid @ c
|
|
.long __irq_invalid @ d
|
|
.long __irq_invalid @ e
|
|
.long __irq_invalid @ f
|
|
|
|
/*
|
|
* Data abort dispatcher
|
|
* Enter in ABT mode, spsr = USR CPSR, lr = USR PC
|
|
*/
|
|
vector_stub dabt, ABT_MODE, 8
|
|
|
|
.long __dabt_usr @ 0 (USR_26 / USR_32)
|
|
.long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
|
|
.long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
|
|
.long __dabt_svc @ 3 (SVC_26 / SVC_32)
|
|
.long __dabt_invalid @ 4
|
|
.long __dabt_invalid @ 5
|
|
.long __dabt_invalid @ 6
|
|
.long __dabt_invalid @ 7
|
|
.long __dabt_invalid @ 8
|
|
.long __dabt_invalid @ 9
|
|
.long __dabt_invalid @ a
|
|
.long __dabt_invalid @ b
|
|
.long __dabt_invalid @ c
|
|
.long __dabt_invalid @ d
|
|
.long __dabt_invalid @ e
|
|
.long __dabt_invalid @ f
|
|
|
|
/*
|
|
* Prefetch abort dispatcher
|
|
* Enter in ABT mode, spsr = USR CPSR, lr = USR PC
|
|
*/
|
|
vector_stub pabt, ABT_MODE, 4
|
|
|
|
.long __pabt_usr @ 0 (USR_26 / USR_32)
|
|
.long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
|
|
.long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
|
|
.long __pabt_svc @ 3 (SVC_26 / SVC_32)
|
|
.long __pabt_invalid @ 4
|
|
.long __pabt_invalid @ 5
|
|
.long __pabt_invalid @ 6
|
|
.long __pabt_invalid @ 7
|
|
.long __pabt_invalid @ 8
|
|
.long __pabt_invalid @ 9
|
|
.long __pabt_invalid @ a
|
|
.long __pabt_invalid @ b
|
|
.long __pabt_invalid @ c
|
|
.long __pabt_invalid @ d
|
|
.long __pabt_invalid @ e
|
|
.long __pabt_invalid @ f
|
|
|
|
/*
|
|
* Undef instr entry dispatcher
|
|
* Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
|
|
*/
|
|
vector_stub und, UND_MODE
|
|
|
|
.long __und_usr @ 0 (USR_26 / USR_32)
|
|
.long __und_invalid @ 1 (FIQ_26 / FIQ_32)
|
|
.long __und_invalid @ 2 (IRQ_26 / IRQ_32)
|
|
.long __und_svc @ 3 (SVC_26 / SVC_32)
|
|
.long __und_invalid @ 4
|
|
.long __und_invalid @ 5
|
|
.long __und_invalid @ 6
|
|
.long __und_invalid @ 7
|
|
.long __und_invalid @ 8
|
|
.long __und_invalid @ 9
|
|
.long __und_invalid @ a
|
|
.long __und_invalid @ b
|
|
.long __und_invalid @ c
|
|
.long __und_invalid @ d
|
|
.long __und_invalid @ e
|
|
.long __und_invalid @ f
|
|
|
|
.align 5
|
|
|
|
/*=============================================================================
|
|
* Undefined FIQs
|
|
*-----------------------------------------------------------------------------
|
|
* Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
|
|
* MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
|
|
* Basically to switch modes, we *HAVE* to clobber one register... brain
|
|
* damage alert! I don't think that we can execute any code in here in any
|
|
* other mode than FIQ... Ok you can switch to another mode, but you can't
|
|
* get out of that mode without clobbering one register.
|
|
*/
|
|
vector_fiq:
|
|
disable_fiq
|
|
subs pc, lr, #4
|
|
|
|
/*=============================================================================
|
|
* Address exception handler
|
|
*-----------------------------------------------------------------------------
|
|
* These aren't too critical.
|
|
* (they're not supposed to happen, and won't happen in 32-bit data mode).
|
|
*/
|
|
|
|
vector_addrexcptn:
|
|
b vector_addrexcptn
|
|
|
|
/*
|
|
* We group all the following data together to optimise
|
|
* for CPUs with separate I & D caches.
|
|
*/
|
|
.align 5
|
|
|
|
.LCvswi:
|
|
.word vector_swi
|
|
|
|
.globl __stubs_end
|
|
__stubs_end:
|
|
|
|
.equ stubs_offset, __vectors_start + 0x200 - __stubs_start
|
|
|
|
.globl __vectors_start
|
|
__vectors_start:
|
|
ARM( swi SYS_ERROR0 )
|
|
THUMB( svc #0 )
|
|
THUMB( nop )
|
|
W(b) vector_und + stubs_offset
|
|
W(ldr) pc, .LCvswi + stubs_offset
|
|
W(b) vector_pabt + stubs_offset
|
|
W(b) vector_dabt + stubs_offset
|
|
W(b) vector_addrexcptn + stubs_offset
|
|
W(b) vector_irq + stubs_offset
|
|
W(b) vector_fiq + stubs_offset
|
|
|
|
.globl __vectors_end
|
|
__vectors_end:
|
|
|
|
.data
|
|
|
|
.globl cr_alignment
|
|
.globl cr_no_alignment
|
|
cr_alignment:
|
|
.space 4
|
|
cr_no_alignment:
|
|
.space 4
|