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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ef2a270592
The L2 cache comes up in a "safe mode" on the PB11MPCore, as it has several issues. This sets it up properly with the right size and associativity, also requiring the outer sync to be disabled for the machine to boot properly. Cc: Russell King <linux@arm.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
682 lines
17 KiB
Plaintext
682 lines
17 KiB
Plaintext
/*
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* Copyright 2015 Linaro Ltd
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "skeleton.dtsi"
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/ {
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model = "ARM RealView PB11MPcore";
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compatible = "arm,realview-pb11mp";
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chosen { };
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aliases {
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serial0 = &pb11mp_serial0;
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serial1 = &pb11mp_serial1;
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serial2 = &pb11mp_serial2;
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serial3 = &pb11mp_serial3;
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};
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memory {
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/*
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* The PB11MPCore has 512 MiB memory @ 0x70000000
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* and the first 256 are also remapped @ 0x00000000
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*/
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reg = <0x70000000 0x20000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "arm,realview-smp";
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MP11_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,arm11mpcore";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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MP11_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,arm11mpcore";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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MP11_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,arm11mpcore";
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reg = <2>;
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next-level-cache = <&L2>;
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};
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MP11_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,arm11mpcore";
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reg = <3>;
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next-level-cache = <&L2>;
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};
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};
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/* Primary TestChip GIC synthesized with the CPU */
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intc_tc11mp: interrupt-controller@1f000100 {
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compatible = "arm,tc11mp-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0x1f001000 0x1000>,
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<0x1f000100 0x100>;
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};
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L2: l2-cache {
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compatible = "arm,l220-cache";
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reg = <0x1f002000 0x1000>;
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interrupt-parent = <&intc_tc11mp>;
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interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
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<0 30 IRQ_TYPE_LEVEL_HIGH>,
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<0 31 IRQ_TYPE_LEVEL_HIGH>;
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cache-unified;
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cache-level = <2>;
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/*
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* Override default cache size, sets and
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* associativity as these may be erroneously set
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* up by boot loader(s), probably for safety
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* since th outer sync operation can cause the
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* cache to hang unless disabled.
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*/
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cache-size = <1048576>; // 1MB
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cache-sets = <4096>;
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cache-line-size = <32>;
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arm,shared-override;
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arm,parity-enable;
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arm,outer-sync-disable;
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};
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scu@1f000000 {
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compatible = "arm,arm11mp-scu";
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reg = <0x1f000000 0x100>;
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};
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timer@1f000600 {
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compatible = "arm,arm11mp-twd-timer";
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reg = <0x1f000600 0x20>;
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interrupt-parent = <&intc_tc11mp>;
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interrupts = <1 13 0xf04>;
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};
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watchdog@1f000620 {
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compatible = "arm,arm11mp-twd-wdt";
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reg = <0x1f000620 0x20>;
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interrupt-parent = <&intc_tc11mp>;
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interrupts = <1 14 0xf04>;
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};
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/* PMU with one IRQ line per core */
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pmu {
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compatible = "arm,arm11mpcore-pmu";
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interrupt-parent = <&intc_tc11mp>;
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interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
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<0 18 IRQ_TYPE_LEVEL_HIGH>,
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<0 19 IRQ_TYPE_LEVEL_HIGH>,
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<0 20 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
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};
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/* The voltage to the MMC card is hardwired at 3.3V */
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vmmc: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "vmmc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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veth: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "veth";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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xtal24mhz: xtal24mhz@24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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refclk32khz: refclk32khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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timclk: timclk@1M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <24>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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mclk: mclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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kmiclk: kmiclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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sspclk: sspclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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uartclk: uartclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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wdogclk: wdogclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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/* FIXME: this actually hangs off the PLL clocks */
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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flash0@40000000 {
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/* 2 * 32MiB NOR Flash memory */
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compatible = "arm,vexpress-flash", "cfi-flash";
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reg = <0x40000000 0x04000000>;
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bank-width = <4>;
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};
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flash1@44000000 {
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// 2 * 32MiB NOR Flash memory
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compatible = "arm,vexpress-flash", "cfi-flash";
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reg = <0x44000000 0x04000000>;
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bank-width = <4>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,realview-pb11mp-soc", "simple-bus";
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regmap = <&pb11mp_syscon>;
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ranges;
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pb11mp_syscon: syscon@10000000 {
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compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
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reg = <0x10000000 0x1000>;
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led@08.0 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x01>;
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label = "versatile:0";
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linux,default-trigger = "heartbeat";
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default-state = "on";
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};
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led@08.1 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x02>;
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label = "versatile:1";
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linux,default-trigger = "mmc0";
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default-state = "off";
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};
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led@08.2 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x04>;
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label = "versatile:2";
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linux,default-trigger = "cpu0";
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default-state = "off";
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};
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led@08.3 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x08>;
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label = "versatile:3";
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linux,default-trigger = "cpu1";
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default-state = "off";
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};
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led@08.4 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x10>;
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label = "versatile:4";
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linux,default-trigger = "cpu2";
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default-state = "off";
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};
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led@08.5 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x20>;
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label = "versatile:5";
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linux,default-trigger = "cpu3";
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default-state = "off";
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};
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led@08.6 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x40>;
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label = "versatile:6";
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default-state = "off";
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};
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led@08.7 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x80>;
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label = "versatile:7";
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default-state = "off";
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};
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oscclk0: osc0@0c {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x0C>;
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clocks = <&xtal24mhz>;
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};
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oscclk1: osc1@10 {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x10>;
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clocks = <&xtal24mhz>;
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};
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oscclk2: osc2@14 {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x14>;
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clocks = <&xtal24mhz>;
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};
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oscclk3: osc3@18 {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x18>;
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clocks = <&xtal24mhz>;
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};
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oscclk4: osc4@1c {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0x1c>;
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clocks = <&xtal24mhz>;
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};
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oscclk5: osc5@d4 {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0xd4>;
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clocks = <&xtal24mhz>;
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};
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oscclk6: osc6@d8 {
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compatible = "arm,syscon-icst307";
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#clock-cells = <0>;
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lock-offset = <0x20>;
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vco-offset = <0xd8>;
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clocks = <&xtal24mhz>;
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};
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};
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sp810_syscon: sysctl@10001000 {
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compatible = "arm,sp810", "arm,primecell";
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reg = <0x10001000 0x1000>;
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clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
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clock-names = "refclk", "timclk", "apb_pclk";
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#clock-cells = <1>;
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clock-output-names = "timerclk0",
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"timerclk1",
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"timerclk2",
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"timerclk3";
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assigned-clocks = <&sp810_syscon 0>,
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<&sp810_syscon 1>,
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<&sp810_syscon 2>,
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<&sp810_syscon 3>;
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assigned-clock-parents = <&timclk>,
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<&timclk>,
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<&timclk>,
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<&timclk>;
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};
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i2c0: i2c@10002000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "arm,versatile-i2c";
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reg = <0x10002000 0x1000>;
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rtc@68 {
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compatible = "dallas,ds1338";
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reg = <0x68>;
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};
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};
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aaci: aaci@10004000 {
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compatible = "arm,pl041", "arm,primecell";
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reg = <0x10004000 0x1000>;
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interrupt-parent = <&intc_tc11mp>;
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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mci: mmcsd@10005000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x10005000 0x1000>;
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interrupt-parent = <&intc_tc11mp>;
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interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
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<0 15 IRQ_TYPE_LEVEL_HIGH>;
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/* Due to frequent FIFO overruns, use just 500 kHz */
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max-frequency = <500000>;
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bus-width = <4>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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clocks = <&mclk>, <&pclk>;
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clock-names = "mclk", "apb_pclk";
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vmmc-supply = <&vmmc>;
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cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
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};
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kmi0: kmi@10006000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x10006000 0x1000>;
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interrupt-parent = <&intc_tc11mp>;
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interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&kmiclk>, <&pclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi1: kmi@10007000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x10007000 0x1000>;
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interrupt-parent = <&intc_tc11mp>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&kmiclk>, <&pclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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pb11mp_serial0: serial@10009000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x10009000 0x1000>;
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interrupt-parent = <&intc_tc11mp>;
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interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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pb11mp_serial1: serial@1000a000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1000a000 0x1000>;
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interrupt-parent = <&intc_tc11mp>;
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interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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pb11mp_serial2: serial@1000b000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1000b000 0x1000>;
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interrupt-parent = <&intc_pb11mp>;
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interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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pb11mp_serial3: serial@1000c000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1000c000 0x1000>;
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interrupt-parent = <&intc_pb11mp>;
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interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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ssp@1000d000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x1000d000 0x1000>;
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interrupt-parent = <&intc_pb11mp>;
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interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sspclk>, <&pclk>;
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clock-names = "SSPCLK", "apb_pclk";
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};
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watchdog@1000f000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x1000f000 0x1000>;
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interrupt-parent = <&intc_pb11mp>;
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&wdogclk>, <&pclk>;
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clock-names = "wdogclk", "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
watchdog@10010000 {
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
reg = <0x10010000 0x1000>;
|
|
interrupt-parent = <&intc_pb11mp>;
|
|
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&wdogclk>, <&pclk>;
|
|
clock-names = "wdogclk", "apb_pclk";
|
|
};
|
|
|
|
timer01: timer@10011000 {
|
|
compatible = "arm,sp804", "arm,primecell";
|
|
reg = <0x10011000 0x1000>;
|
|
interrupt-parent = <&intc_tc11mp>;
|
|
interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
arm,sp804-has-irq = <1>;
|
|
clocks = <&sp810_syscon 0>,
|
|
<&sp810_syscon 1>,
|
|
<&pclk>;
|
|
clock-names = "timerclk0",
|
|
"timerclk1",
|
|
"apb_pclk";
|
|
};
|
|
|
|
timer23: timer@10012000 {
|
|
compatible = "arm,sp804", "arm,primecell";
|
|
reg = <0x10012000 0x1000>;
|
|
interrupt-parent = <&intc_tc11mp>;
|
|
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
arm,sp804-has-irq = <1>;
|
|
clocks = <&sp810_syscon 2>,
|
|
<&sp810_syscon 3>,
|
|
<&pclk>;
|
|
clock-names = "timerclk2",
|
|
"timerclk3",
|
|
"apb_pclk";
|
|
};
|
|
|
|
gpio0: gpio@10013000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x10013000 0x1000>;
|
|
gpio-controller;
|
|
interrupt-parent = <&intc_pb11mp>;
|
|
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pclk>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gpio1: gpio@10014000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x10014000 0x1000>;
|
|
gpio-controller;
|
|
interrupt-parent = <&intc_pb11mp>;
|
|
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pclk>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gpio2: gpio@10015000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x10015000 0x1000>;
|
|
gpio-controller;
|
|
interrupt-parent = <&intc_pb11mp>;
|
|
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pclk>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
rtc: rtc@10017000 {
|
|
compatible = "arm,pl031", "arm,primecell";
|
|
reg = <0x10017000 0x1000>;
|
|
interrupt-parent = <&intc_tc11mp>;
|
|
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pclk>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
timer45: timer@10018000 {
|
|
compatible = "arm,sp804", "arm,primecell";
|
|
reg = <0x10018000 0x1000>;
|
|
clocks = <&timclk>, <&pclk>;
|
|
clock-names = "timer", "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer67: timer@10019000 {
|
|
compatible = "arm,sp804", "arm,primecell";
|
|
reg = <0x10019000 0x1000>;
|
|
clocks = <&timclk>, <&pclk>;
|
|
clock-names = "timer", "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
|
|
clcd@10020000 {
|
|
compatible = "arm,pl111", "arm,primecell";
|
|
reg = <0x10020000 0x1000>;
|
|
interrupt-parent = <&intc_pb11mp>;
|
|
interrupt-names = "combined";
|
|
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&oscclk4>, <&pclk>;
|
|
clock-names = "clcdclk", "apb_pclk";
|
|
max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
|
|
|
|
port {
|
|
clcd_pads: endpoint {
|
|
remote-endpoint = <&clcd_panel>;
|
|
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
|
};
|
|
};
|
|
|
|
panel {
|
|
compatible = "panel-dpi";
|
|
|
|
port {
|
|
clcd_panel: endpoint {
|
|
remote-endpoint = <&clcd_pads>;
|
|
};
|
|
};
|
|
|
|
panel-timing {
|
|
clock-frequency = <63500127>;
|
|
hactive = <1024>;
|
|
hback-porch = <152>;
|
|
hfront-porch = <48>;
|
|
hsync-len = <104>;
|
|
vactive = <768>;
|
|
vback-porch = <23>;
|
|
vfront-porch = <3>;
|
|
vsync-len = <4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/*
|
|
* This GIC on the Platform Baseboard is cascaded off the
|
|
* TestChip GIC
|
|
*/
|
|
intc_pb11mp: interrupt-controller@1e000000 {
|
|
compatible = "arm,arm11mp-gic";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <1>;
|
|
interrupt-controller;
|
|
reg = <0x1e001000 0x1000>,
|
|
<0x1e000000 0x100>;
|
|
interrupt-parent = <&intc_tc11mp>;
|
|
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
/* SMSC 9118 ethernet with PHY and EEPROM */
|
|
ethernet@4e000000 {
|
|
compatible = "smsc,lan9118", "smsc,lan9115";
|
|
reg = <0x4e000000 0x10000>;
|
|
interrupt-parent = <&intc_tc11mp>;
|
|
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy-mode = "mii";
|
|
reg-io-width = <4>;
|
|
smsc,irq-active-high;
|
|
smsc,irq-push-pull;
|
|
vdd33a-supply = <&veth>;
|
|
vddvario-supply = <&veth>;
|
|
};
|
|
|
|
usb@4f000000 {
|
|
compatible = "nxp,usb-isp1761";
|
|
reg = <0x4f000000 0x20000>;
|
|
interrupt-parent = <&intc_tc11mp>;
|
|
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
port1-otg;
|
|
};
|
|
};
|
|
};
|