Anusha Srivatsa 08cadae8e1 i915/dp/fec: Cache the FEC_CAPABLE DPCD register ... Similar to DSC DPCD registers, let us cache FEC_CAPABLE register to avoid using stale values. With this we can avoid aux reads everytime and instead read the cached values. v2: Avoid using memset and array for a single field. (Manasi,Jani) v3: Print FEC CAPABILITY value. (Manasi) Suggested-by: Jani Nikula <jani.nikula@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181102041455.15818-1-anusha.srivatsa@intel.com		2018-11-02 18:21:21 -07:00
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drm	i915/dp/fec: Cache the FEC_CAPABLE DPCD register	2018-11-02 18:21:21 -07:00
host1x	gpu: host1x: Detach Host1x from IOMMU DMA domain on arm32	2018-09-26 17:11:14 +02:00
ipu-v3
vga	ALSA: hda - Enable runtime PM only for discrete GPU	2018-09-13 17:58:30 +02:00
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