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405990c7e8
Needed to properly decode the RAM code register. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
15 lines
696 B
Plaintext
15 lines
696 B
Plaintext
NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block
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Required properties:
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- compatible : For Tegra20, must be "nvidia,tegra20-apbmisc". For Tegra30,
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must be "nvidia,tegra30-apbmisc". Otherwise, must contain
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"nvidia,<chip>-apbmisc", plus one of the above, where <chip> is tegra114,
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tegra124, tegra132.
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- reg: Should contain 2 entries: the first entry gives the physical address
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and length of the registers which contain revision and debug features.
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The second entry gives the physical address and length of the
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registers indicating the strapping options.
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Optional properties:
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- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).
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