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This commit adds the Device Tree binding description for the PIC interrupt controller available in the ARM64 Marvell Armada 7K/8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/1470408921-447-2-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
26 lines
887 B
Plaintext
26 lines
887 B
Plaintext
Marvell Armada 7K/8K PIC Interrupt controller
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This is the Device Tree binding for the PIC, a secondary interrupt
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controller available on the Marvell Armada 7K/8K ARM64 SoCs, and
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typically connected to the GIC as the primary interrupt controller.
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Required properties:
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- compatible: should be "marvell,armada-8k-pic"
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: the number of cells to define interrupts on this
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controller. Should be 1
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- reg: the register area for the PIC interrupt controller
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- interrupts: the interrupt to the primary interrupt controller,
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typically the GIC
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Example:
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pic: interrupt-controller@3f0100 {
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compatible = "marvell,armada-8k-pic";
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reg = <0x3f0100 0x10>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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