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d398665064
add mt2701-afe-pcm.txt and mt2701-cs42448.txt for mt2701 Signed-off-by: Garlic Tseng <garlic.tseng@mediatek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
151 lines
4.3 KiB
Plaintext
151 lines
4.3 KiB
Plaintext
Mediatek AFE PCM controller for mt2701
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Required properties:
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- compatible = "mediatek,mt2701-audio";
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- reg: register location and size
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- interrupts: Should contain AFE interrupt
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- clock-names: should have these clock names:
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"infra_sys_audio_clk",
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"top_audio_mux1_sel",
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"top_audio_mux2_sel",
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"top_audio_mux1_div",
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"top_audio_mux2_div",
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"top_audio_48k_timing",
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"top_audio_44k_timing",
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"top_audpll_mux_sel",
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"top_apll_sel",
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"top_aud1_pll_98M",
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"top_aud2_pll_90M",
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"top_hadds2_pll_98M",
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"top_hadds2_pll_294M",
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"top_audpll",
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"top_audpll_d4",
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"top_audpll_d8",
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"top_audpll_d16",
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"top_audpll_d24",
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"top_audintbus_sel",
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"clk_26m",
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"top_syspll1_d4",
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"top_aud_k1_src_sel",
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"top_aud_k2_src_sel",
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"top_aud_k3_src_sel",
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"top_aud_k4_src_sel",
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"top_aud_k5_src_sel",
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"top_aud_k6_src_sel",
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"top_aud_k1_src_div",
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"top_aud_k2_src_div",
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"top_aud_k3_src_div",
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"top_aud_k4_src_div",
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"top_aud_k5_src_div",
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"top_aud_k6_src_div",
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"top_aud_i2s1_mclk",
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"top_aud_i2s2_mclk",
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"top_aud_i2s3_mclk",
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"top_aud_i2s4_mclk",
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"top_aud_i2s5_mclk",
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"top_aud_i2s6_mclk",
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"top_asm_m_sel",
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"top_asm_h_sel",
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"top_univpll2_d4",
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"top_univpll2_d2",
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"top_syspll_d5";
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Example:
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afe: mt2701-afe-pcm@11220000 {
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compatible = "mediatek,mt2701-audio";
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reg = <0 0x11220000 0 0x2000>,
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<0 0x112A0000 0 0x20000>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_AUDIO>,
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<&topckgen CLK_TOP_AUD_MUX1_SEL>,
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<&topckgen CLK_TOP_AUD_MUX2_SEL>,
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<&topckgen CLK_TOP_AUD_MUX1_DIV>,
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<&topckgen CLK_TOP_AUD_MUX2_DIV>,
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<&topckgen CLK_TOP_AUD_48K_TIMING>,
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<&topckgen CLK_TOP_AUD_44K_TIMING>,
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<&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
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<&topckgen CLK_TOP_APLL_SEL>,
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<&topckgen CLK_TOP_AUD1PLL_98M>,
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<&topckgen CLK_TOP_AUD2PLL_90M>,
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<&topckgen CLK_TOP_HADDS2PLL_98M>,
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<&topckgen CLK_TOP_HADDS2PLL_294M>,
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<&topckgen CLK_TOP_AUDPLL>,
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<&topckgen CLK_TOP_AUDPLL_D4>,
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<&topckgen CLK_TOP_AUDPLL_D8>,
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<&topckgen CLK_TOP_AUDPLL_D16>,
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<&topckgen CLK_TOP_AUDPLL_D24>,
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<&topckgen CLK_TOP_AUDINTBUS_SEL>,
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<&clk26m>,
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<&topckgen CLK_TOP_SYSPLL1_D4>,
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<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S5_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S6_MCLK>,
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<&topckgen CLK_TOP_ASM_M_SEL>,
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<&topckgen CLK_TOP_ASM_H_SEL>,
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<&topckgen CLK_TOP_UNIVPLL2_D4>,
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<&topckgen CLK_TOP_UNIVPLL2_D2>,
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<&topckgen CLK_TOP_SYSPLL_D5>;
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clock-names = "infra_sys_audio_clk",
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"top_audio_mux1_sel",
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"top_audio_mux2_sel",
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"top_audio_mux1_div",
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"top_audio_mux2_div",
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"top_audio_48k_timing",
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"top_audio_44k_timing",
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"top_audpll_mux_sel",
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"top_apll_sel",
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"top_aud1_pll_98M",
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"top_aud2_pll_90M",
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"top_hadds2_pll_98M",
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"top_hadds2_pll_294M",
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"top_audpll",
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"top_audpll_d4",
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"top_audpll_d8",
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"top_audpll_d16",
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"top_audpll_d24",
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"top_audintbus_sel",
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"clk_26m",
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"top_syspll1_d4",
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"top_aud_k1_src_sel",
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"top_aud_k2_src_sel",
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"top_aud_k3_src_sel",
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"top_aud_k4_src_sel",
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"top_aud_k5_src_sel",
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"top_aud_k6_src_sel",
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"top_aud_k1_src_div",
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"top_aud_k2_src_div",
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"top_aud_k3_src_div",
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"top_aud_k4_src_div",
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"top_aud_k5_src_div",
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"top_aud_k6_src_div",
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"top_aud_i2s1_mclk",
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"top_aud_i2s2_mclk",
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"top_aud_i2s3_mclk",
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"top_aud_i2s4_mclk",
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"top_aud_i2s5_mclk",
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"top_aud_i2s6_mclk",
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"top_asm_m_sel",
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"top_asm_h_sel",
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"top_univpll2_d4",
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"top_univpll2_d2",
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"top_syspll_d5";
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};
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