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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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bca10b906f
Handling System MMUs with an identifier is not flexible to manage System MMU platform devices because of the following reasons: 1. A device driver which needs to handle System MMU must know the ID. 2. A System MMU may not present in some implementations of Exynos family. 3. Handling System MMU with IOMMU API does not require an ID. This patch is the result of removing ID of System MMUs. Instead, a device driver that needs to handle its System MMU must use IOMMU API while its descriptor of platform device is given. This patch also includes the following enhancements: - A System MMU device becomes a child if its power domain device. - clkdev Signed-off-by: KyongHo Cho <pullip.cho@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
275 lines
9.2 KiB
C
275 lines
9.2 KiB
C
/* linux/arch/arm/mach-exynos/dev-sysmmu.c
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*
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* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - System MMU support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <plat/cpu.h>
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#include <mach/map.h>
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#include <mach/irqs.h>
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#include <mach/sysmmu.h>
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static u64 exynos_sysmmu_dma_mask = DMA_BIT_MASK(32);
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#define SYSMMU_PLATFORM_DEVICE(ipname, devid) \
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static struct sysmmu_platform_data platdata_##ipname = { \
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.dbgname = #ipname, \
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}; \
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struct platform_device SYSMMU_PLATDEV(ipname) = \
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{ \
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.name = SYSMMU_DEVNAME_BASE, \
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.id = devid, \
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.dev = { \
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.dma_mask = &exynos_sysmmu_dma_mask, \
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.coherent_dma_mask = DMA_BIT_MASK(32), \
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.platform_data = &platdata_##ipname, \
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}, \
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}
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SYSMMU_PLATFORM_DEVICE(mfc_l, 0);
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SYSMMU_PLATFORM_DEVICE(mfc_r, 1);
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SYSMMU_PLATFORM_DEVICE(tv, 2);
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SYSMMU_PLATFORM_DEVICE(jpeg, 3);
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SYSMMU_PLATFORM_DEVICE(rot, 4);
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SYSMMU_PLATFORM_DEVICE(fimc0, 5); /* fimc* and gsc* exist exclusively */
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SYSMMU_PLATFORM_DEVICE(fimc1, 6);
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SYSMMU_PLATFORM_DEVICE(fimc2, 7);
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SYSMMU_PLATFORM_DEVICE(fimc3, 8);
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SYSMMU_PLATFORM_DEVICE(gsc0, 5);
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SYSMMU_PLATFORM_DEVICE(gsc1, 6);
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SYSMMU_PLATFORM_DEVICE(gsc2, 7);
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SYSMMU_PLATFORM_DEVICE(gsc3, 8);
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SYSMMU_PLATFORM_DEVICE(isp, 9);
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SYSMMU_PLATFORM_DEVICE(fimd0, 10);
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SYSMMU_PLATFORM_DEVICE(fimd1, 11);
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SYSMMU_PLATFORM_DEVICE(camif0, 12);
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SYSMMU_PLATFORM_DEVICE(camif1, 13);
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SYSMMU_PLATFORM_DEVICE(2d, 14);
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#define SYSMMU_RESOURCE_NAME(core, ipname) sysmmures_##core##_##ipname
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#define SYSMMU_RESOURCE(core, ipname) \
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static struct resource SYSMMU_RESOURCE_NAME(core, ipname)[] __initdata =
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#define DEFINE_SYSMMU_RESOURCE(core, mem, irq) \
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DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem), \
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DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
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#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq) \
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SYSMMU_RESOURCE(core, ipname) { \
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DEFINE_SYSMMU_RESOURCE(core, mem, irq) \
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}
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struct sysmmu_resource_map {
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struct platform_device *pdev;
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struct resource *res;
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u32 rnum;
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struct device *pdd;
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char *clocknames;
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};
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#define SYSMMU_RESOURCE_MAPPING(core, ipname, resname) { \
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.pdev = &SYSMMU_PLATDEV(ipname), \
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.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
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.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
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.clocknames = SYSMMU_CLOCK_NAME, \
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}
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#define SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata) { \
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.pdev = &SYSMMU_PLATDEV(ipname), \
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.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
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.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
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.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, \
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}
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#ifdef CONFIG_EXYNOS_DEV_PD
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#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) { \
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.pdev = &SYSMMU_PLATDEV(ipname), \
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.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
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.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
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.clocknames = SYSMMU_CLOCK_NAME, \
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.pdd = &exynos##core##_device_pd[pd].dev, \
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}
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#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) {\
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.pdev = &SYSMMU_PLATDEV(ipname), \
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.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
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.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
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.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, \
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.pdd = &exynos##core##_device_pd[pd].dev, \
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}
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#else
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#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) \
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SYSMMU_RESOURCE_MAPPING(core, ipname, resname)
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#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) \
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SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata)
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#endif /* CONFIG_EXYNOS_DEV_PD */
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#ifdef CONFIG_ARCH_EXYNOS4
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc0, FIMC0, FIMC0);
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc1, FIMC1, FIMC1);
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc2, FIMC2, FIMC2);
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc3, FIMC3, FIMC3);
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, jpeg, JPEG, JPEG);
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d, G2D, 2D);
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, tv, TV, TV_M0);
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d_acp, 2D_ACP, 2D);
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, rot, ROTATOR, ROTATOR);
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd0, FIMD0, LCD0_M0);
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd1, FIMD1, LCD1_M1);
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite0, FIMC_LITE0, FIMC_LITE0);
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite1, FIMC_LITE1, FIMC_LITE1);
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_r, MFC_R, MFC_M0);
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SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_l, MFC_L, MFC_M1);
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SYSMMU_RESOURCE(EXYNOS4, isp) {
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DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_ISP, FIMC_ISP),
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DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_DRC, FIMC_DRC),
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DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_FD, FIMC_FD),
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DEFINE_SYSMMU_RESOURCE(EXYNOS4, ISPCPU, FIMC_CX),
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};
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static struct sysmmu_resource_map sysmmu_resmap4[] __initdata = {
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SYSMMU_RESOURCE_MAPPING_PD(4, fimc0, fimc0, PD_CAM),
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SYSMMU_RESOURCE_MAPPING_PD(4, fimc1, fimc1, PD_CAM),
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SYSMMU_RESOURCE_MAPPING_PD(4, fimc2, fimc2, PD_CAM),
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SYSMMU_RESOURCE_MAPPING_PD(4, fimc3, fimc3, PD_CAM),
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SYSMMU_RESOURCE_MAPPING_PD(4, tv, tv, PD_TV),
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SYSMMU_RESOURCE_MAPPING_PD(4, mfc_r, mfc_r, PD_MFC),
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SYSMMU_RESOURCE_MAPPING_PD(4, mfc_l, mfc_l, PD_MFC),
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SYSMMU_RESOURCE_MAPPING_PD(4, rot, rot, PD_LCD0),
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SYSMMU_RESOURCE_MAPPING_PD(4, jpeg, jpeg, PD_CAM),
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SYSMMU_RESOURCE_MAPPING_PD(4, fimd0, fimd0, PD_LCD0),
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};
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static struct sysmmu_resource_map sysmmu_resmap4210[] __initdata = {
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SYSMMU_RESOURCE_MAPPING_PD(4, 2d, 2d, PD_LCD0),
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SYSMMU_RESOURCE_MAPPING_PD(4, fimd1, fimd1, PD_LCD1),
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};
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static struct sysmmu_resource_map sysmmu_resmap4212[] __initdata = {
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SYSMMU_RESOURCE_MAPPING(4, 2d, 2d_acp),
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SYSMMU_RESOURCE_MAPPING_PD(4, camif0, flite0, PD_ISP),
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SYSMMU_RESOURCE_MAPPING_PD(4, camif1, flite1, PD_ISP),
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SYSMMU_RESOURCE_MAPPING_PD(4, isp, isp, PD_ISP),
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};
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#endif /* CONFIG_ARCH_EXYNOS4 */
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#ifdef CONFIG_ARCH_EXYNOS5
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SYSMMU_RESOURCE_DEFINE(EXYNOS5, jpeg, JPEG, JPEG);
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SYSMMU_RESOURCE_DEFINE(EXYNOS5, fimd1, FIMD1, FIMD1);
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SYSMMU_RESOURCE_DEFINE(EXYNOS5, 2d, 2D, 2D);
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SYSMMU_RESOURCE_DEFINE(EXYNOS5, rot, ROTATOR, ROTATOR);
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SYSMMU_RESOURCE_DEFINE(EXYNOS5, tv, TV, TV);
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SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite0, LITE0, LITE0);
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SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite1, LITE1, LITE1);
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SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc0, GSC0, GSC0);
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SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc1, GSC1, GSC1);
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SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc2, GSC2, GSC2);
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SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc3, GSC3, GSC3);
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SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_r, MFC_R, MFC_R);
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SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_l, MFC_L, MFC_L);
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SYSMMU_RESOURCE(EXYNOS5, isp) {
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DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISP, ISP),
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DEFINE_SYSMMU_RESOURCE(EXYNOS5, DRC, DRC),
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DEFINE_SYSMMU_RESOURCE(EXYNOS5, FD, FD),
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DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISPCPU, MCUISP),
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DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERC, SCALERCISP),
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DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERP, SCALERPISP),
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DEFINE_SYSMMU_RESOURCE(EXYNOS5, ODC, ODC),
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DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS0, DIS0),
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DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS1, DIS1),
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DEFINE_SYSMMU_RESOURCE(EXYNOS5, 3DNR, 3DNR),
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};
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static struct sysmmu_resource_map sysmmu_resmap5[] __initdata = {
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SYSMMU_RESOURCE_MAPPING(5, jpeg, jpeg),
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SYSMMU_RESOURCE_MAPPING(5, fimd1, fimd1),
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SYSMMU_RESOURCE_MAPPING(5, 2d, 2d),
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SYSMMU_RESOURCE_MAPPING(5, rot, rot),
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SYSMMU_RESOURCE_MAPPING_PD(5, tv, tv, PD_DISP1),
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SYSMMU_RESOURCE_MAPPING_PD(5, camif0, flite0, PD_GSCL),
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SYSMMU_RESOURCE_MAPPING_PD(5, camif1, flite1, PD_GSCL),
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SYSMMU_RESOURCE_MAPPING_PD(5, gsc0, gsc0, PD_GSCL),
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SYSMMU_RESOURCE_MAPPING_PD(5, gsc1, gsc1, PD_GSCL),
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SYSMMU_RESOURCE_MAPPING_PD(5, gsc2, gsc2, PD_GSCL),
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SYSMMU_RESOURCE_MAPPING_PD(5, gsc3, gsc3, PD_GSCL),
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SYSMMU_RESOURCE_MAPPING_PD(5, mfc_r, mfc_r, PD_MFC),
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SYSMMU_RESOURCE_MAPPING_PD(5, mfc_l, mfc_l, PD_MFC),
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SYSMMU_RESOURCE_MAPPING_MCPD(5, isp, isp, PD_ISP, mc_platdata),
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};
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#endif /* CONFIG_ARCH_EXYNOS5 */
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static int __init init_sysmmu_platform_device(void)
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{
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int i, j;
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struct sysmmu_resource_map *resmap[2] = {NULL, NULL};
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int nmap[2] = {0, 0};
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#ifdef CONFIG_ARCH_EXYNOS5
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if (soc_is_exynos5250()) {
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resmap[0] = sysmmu_resmap5;
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nmap[0] = ARRAY_SIZE(sysmmu_resmap5);
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nmap[1] = 0;
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}
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#endif
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#ifdef CONFIG_ARCH_EXYNOS4
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if (resmap[0] == NULL) {
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resmap[0] = sysmmu_resmap4;
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nmap[0] = ARRAY_SIZE(sysmmu_resmap4);
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}
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if (soc_is_exynos4210()) {
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resmap[1] = sysmmu_resmap4210;
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nmap[1] = ARRAY_SIZE(sysmmu_resmap4210);
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}
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if (soc_is_exynos4412() || soc_is_exynos4212()) {
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resmap[1] = sysmmu_resmap4212;
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nmap[1] = ARRAY_SIZE(sysmmu_resmap4212);
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}
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#endif
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for (j = 0; j < 2; j++) {
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for (i = 0; i < nmap[j]; i++) {
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struct sysmmu_resource_map *map;
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struct sysmmu_platform_data *platdata;
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map = &resmap[j][i];
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map->pdev->dev.parent = map->pdd;
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platdata = map->pdev->dev.platform_data;
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platdata->clockname = map->clocknames;
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if (platform_device_add_resources(map->pdev, map->res,
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map->rnum)) {
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pr_err("%s: Failed to add device resources for "
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"%s.%d\n", __func__,
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map->pdev->name, map->pdev->id);
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continue;
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}
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if (platform_device_register(map->pdev)) {
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pr_err("%s: Failed to register %s.%d\n",
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__func__, map->pdev->name,
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map->pdev->id);
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}
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}
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}
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return 0;
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}
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arch_initcall(init_sysmmu_platform_device);
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