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c390b0363d
drivers/usb/dwc3/ep0.c: In function `__dwc3_ep0_do_control_data': drivers/usb/dwc3/ep0.c:905: error: `typeof' applied to a bit-field Looks like a gcc-3.4.5/sparc64 bug. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Felipe Balbi <balbi@ti.com>
1056 lines
26 KiB
C
1056 lines
26 KiB
C
/**
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* ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2, as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/dma-mapping.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/composite.h>
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#include "core.h"
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#include "gadget.h"
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#include "io.h"
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static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
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static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
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struct dwc3_ep *dep, struct dwc3_request *req);
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static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
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{
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switch (state) {
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case EP0_UNCONNECTED:
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return "Unconnected";
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case EP0_SETUP_PHASE:
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return "Setup Phase";
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case EP0_DATA_PHASE:
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return "Data Phase";
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case EP0_STATUS_PHASE:
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return "Status Phase";
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default:
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return "UNKNOWN";
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}
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}
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static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
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u32 len, u32 type)
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{
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struct dwc3_gadget_ep_cmd_params params;
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struct dwc3_trb *trb;
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struct dwc3_ep *dep;
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int ret;
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dep = dwc->eps[epnum];
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if (dep->flags & DWC3_EP_BUSY) {
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dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
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return 0;
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}
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trb = dwc->ep0_trb;
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trb->bpl = lower_32_bits(buf_dma);
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trb->bph = upper_32_bits(buf_dma);
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trb->size = len;
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trb->ctrl = type;
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trb->ctrl |= (DWC3_TRB_CTRL_HWO
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| DWC3_TRB_CTRL_LST
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| DWC3_TRB_CTRL_IOC
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| DWC3_TRB_CTRL_ISP_IMI);
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memset(¶ms, 0, sizeof(params));
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params.param0 = upper_32_bits(dwc->ep0_trb_addr);
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params.param1 = lower_32_bits(dwc->ep0_trb_addr);
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ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
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DWC3_DEPCMD_STARTTRANSFER, ¶ms);
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if (ret < 0) {
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dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
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return ret;
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}
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dep->flags |= DWC3_EP_BUSY;
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dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
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dep->number);
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dwc->ep0_next_event = DWC3_EP0_COMPLETE;
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return 0;
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}
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static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
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struct dwc3_request *req)
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{
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struct dwc3 *dwc = dep->dwc;
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req->request.actual = 0;
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req->request.status = -EINPROGRESS;
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req->epnum = dep->number;
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list_add_tail(&req->list, &dep->request_list);
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/*
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* Gadget driver might not be quick enough to queue a request
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* before we get a Transfer Not Ready event on this endpoint.
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*
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* In that case, we will set DWC3_EP_PENDING_REQUEST. When that
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* flag is set, it's telling us that as soon as Gadget queues the
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* required request, we should kick the transfer here because the
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* IRQ we were waiting for is long gone.
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*/
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if (dep->flags & DWC3_EP_PENDING_REQUEST) {
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unsigned direction;
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direction = !!(dep->flags & DWC3_EP0_DIR_IN);
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if (dwc->ep0state != EP0_DATA_PHASE) {
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dev_WARN(dwc->dev, "Unexpected pending request\n");
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return 0;
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}
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__dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
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dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
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DWC3_EP0_DIR_IN);
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return 0;
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}
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/*
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* In case gadget driver asked us to delay the STATUS phase,
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* handle it here.
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*/
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if (dwc->delayed_status) {
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unsigned direction;
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direction = !dwc->ep0_expect_in;
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dwc->delayed_status = false;
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if (dwc->ep0state == EP0_STATUS_PHASE)
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__dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
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else
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dev_dbg(dwc->dev, "too early for delayed status\n");
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return 0;
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}
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/*
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* Unfortunately we have uncovered a limitation wrt the Data Phase.
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*
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* Section 9.4 says we can wait for the XferNotReady(DATA) event to
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* come before issueing Start Transfer command, but if we do, we will
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* miss situations where the host starts another SETUP phase instead of
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* the DATA phase. Such cases happen at least on TD.7.6 of the Link
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* Layer Compliance Suite.
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*
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* The problem surfaces due to the fact that in case of back-to-back
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* SETUP packets there will be no XferNotReady(DATA) generated and we
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* will be stuck waiting for XferNotReady(DATA) forever.
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*
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* By looking at tables 9-13 and 9-14 of the Databook, we can see that
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* it tells us to start Data Phase right away. It also mentions that if
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* we receive a SETUP phase instead of the DATA phase, core will issue
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* XferComplete for the DATA phase, before actually initiating it in
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* the wire, with the TRB's status set to "SETUP_PENDING". Such status
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* can only be used to print some debugging logs, as the core expects
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* us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
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* just so it completes right away, without transferring anything and,
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* only then, we can go back to the SETUP phase.
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*
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* Because of this scenario, SNPS decided to change the programming
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* model of control transfers and support on-demand transfers only for
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* the STATUS phase. To fix the issue we have now, we will always wait
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* for gadget driver to queue the DATA phase's struct usb_request, then
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* start it right away.
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*
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* If we're actually in a 2-stage transfer, we will wait for
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* XferNotReady(STATUS).
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*/
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if (dwc->three_stage_setup) {
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unsigned direction;
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direction = dwc->ep0_expect_in;
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dwc->ep0state = EP0_DATA_PHASE;
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__dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
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dep->flags &= ~DWC3_EP0_DIR_IN;
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}
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return 0;
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}
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int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
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gfp_t gfp_flags)
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{
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struct dwc3_request *req = to_dwc3_request(request);
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struct dwc3_ep *dep = to_dwc3_ep(ep);
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struct dwc3 *dwc = dep->dwc;
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&dwc->lock, flags);
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if (!dep->endpoint.desc) {
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dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
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request, dep->name);
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ret = -ESHUTDOWN;
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goto out;
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}
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/* we share one TRB for ep0/1 */
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if (!list_empty(&dep->request_list)) {
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ret = -EBUSY;
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goto out;
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}
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dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
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request, dep->name, request->length,
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dwc3_ep0_state_string(dwc->ep0state));
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ret = __dwc3_gadget_ep0_queue(dep, req);
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out:
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spin_unlock_irqrestore(&dwc->lock, flags);
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return ret;
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}
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static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
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{
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struct dwc3_ep *dep;
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/* reinitialize physical ep1 */
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dep = dwc->eps[1];
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dep->flags = DWC3_EP_ENABLED;
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/* stall is always issued on EP0 */
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dep = dwc->eps[0];
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__dwc3_gadget_ep_set_halt(dep, 1);
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dep->flags = DWC3_EP_ENABLED;
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dwc->delayed_status = false;
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if (!list_empty(&dep->request_list)) {
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struct dwc3_request *req;
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req = next_request(&dep->request_list);
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dwc3_gadget_giveback(dep, req, -ECONNRESET);
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}
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dwc->ep0state = EP0_SETUP_PHASE;
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dwc3_ep0_out_start(dwc);
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}
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int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
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{
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struct dwc3_ep *dep = to_dwc3_ep(ep);
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struct dwc3 *dwc = dep->dwc;
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dwc3_ep0_stall_and_restart(dwc);
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return 0;
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}
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void dwc3_ep0_out_start(struct dwc3 *dwc)
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{
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int ret;
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ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
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DWC3_TRBCTL_CONTROL_SETUP);
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WARN_ON(ret < 0);
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}
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static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
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{
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struct dwc3_ep *dep;
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u32 windex = le16_to_cpu(wIndex_le);
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u32 epnum;
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epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
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if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
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epnum |= 1;
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dep = dwc->eps[epnum];
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if (dep->flags & DWC3_EP_ENABLED)
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return dep;
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return NULL;
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}
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static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
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{
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}
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/*
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* ch 9.4.5
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*/
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static int dwc3_ep0_handle_status(struct dwc3 *dwc,
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struct usb_ctrlrequest *ctrl)
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{
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struct dwc3_ep *dep;
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u32 recip;
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u32 reg;
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u16 usb_status = 0;
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__le16 *response_pkt;
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recip = ctrl->bRequestType & USB_RECIP_MASK;
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switch (recip) {
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case USB_RECIP_DEVICE:
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/*
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* LTM will be set once we know how to set this in HW.
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*/
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usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
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|
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if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
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reg = dwc3_readl(dwc->regs, DWC3_DCTL);
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if (reg & DWC3_DCTL_INITU1ENA)
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usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
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if (reg & DWC3_DCTL_INITU2ENA)
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usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
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}
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break;
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|
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case USB_RECIP_INTERFACE:
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/*
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* Function Remote Wake Capable D0
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* Function Remote Wakeup D1
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*/
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break;
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|
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case USB_RECIP_ENDPOINT:
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dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
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if (!dep)
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return -EINVAL;
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|
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if (dep->flags & DWC3_EP_STALL)
|
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usb_status = 1 << USB_ENDPOINT_HALT;
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break;
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default:
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return -EINVAL;
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};
|
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|
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response_pkt = (__le16 *) dwc->setup_buf;
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*response_pkt = cpu_to_le16(usb_status);
|
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|
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dep = dwc->eps[0];
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dwc->ep0_usb_req.dep = dep;
|
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dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
|
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dwc->ep0_usb_req.request.buf = dwc->setup_buf;
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dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
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|
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return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
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}
|
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|
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static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
|
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struct usb_ctrlrequest *ctrl, int set)
|
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{
|
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struct dwc3_ep *dep;
|
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u32 recip;
|
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u32 wValue;
|
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u32 wIndex;
|
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u32 reg;
|
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int ret;
|
|
|
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wValue = le16_to_cpu(ctrl->wValue);
|
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wIndex = le16_to_cpu(ctrl->wIndex);
|
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recip = ctrl->bRequestType & USB_RECIP_MASK;
|
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switch (recip) {
|
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case USB_RECIP_DEVICE:
|
|
|
|
switch (wValue) {
|
|
case USB_DEVICE_REMOTE_WAKEUP:
|
|
break;
|
|
/*
|
|
* 9.4.1 says only only for SS, in AddressState only for
|
|
* default control pipe
|
|
*/
|
|
case USB_DEVICE_U1_ENABLE:
|
|
if (dwc->dev_state != DWC3_CONFIGURED_STATE)
|
|
return -EINVAL;
|
|
if (dwc->speed != DWC3_DSTS_SUPERSPEED)
|
|
return -EINVAL;
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
if (set)
|
|
reg |= DWC3_DCTL_INITU1ENA;
|
|
else
|
|
reg &= ~DWC3_DCTL_INITU1ENA;
|
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dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
break;
|
|
|
|
case USB_DEVICE_U2_ENABLE:
|
|
if (dwc->dev_state != DWC3_CONFIGURED_STATE)
|
|
return -EINVAL;
|
|
if (dwc->speed != DWC3_DSTS_SUPERSPEED)
|
|
return -EINVAL;
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
if (set)
|
|
reg |= DWC3_DCTL_INITU2ENA;
|
|
else
|
|
reg &= ~DWC3_DCTL_INITU2ENA;
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
break;
|
|
|
|
case USB_DEVICE_LTM_ENABLE:
|
|
return -EINVAL;
|
|
break;
|
|
|
|
case USB_DEVICE_TEST_MODE:
|
|
if ((wIndex & 0xff) != 0)
|
|
return -EINVAL;
|
|
if (!set)
|
|
return -EINVAL;
|
|
|
|
dwc->test_mode_nr = wIndex >> 8;
|
|
dwc->test_mode = true;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
|
|
case USB_RECIP_INTERFACE:
|
|
switch (wValue) {
|
|
case USB_INTRF_FUNC_SUSPEND:
|
|
if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
|
|
/* XXX enable Low power suspend */
|
|
;
|
|
if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
|
|
/* XXX enable remote wakeup */
|
|
;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
|
|
case USB_RECIP_ENDPOINT:
|
|
switch (wValue) {
|
|
case USB_ENDPOINT_HALT:
|
|
dep = dwc3_wIndex_to_dep(dwc, wIndex);
|
|
if (!dep)
|
|
return -EINVAL;
|
|
ret = __dwc3_gadget_ep_set_halt(dep, set);
|
|
if (ret)
|
|
return -EINVAL;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
};
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
|
|
{
|
|
u32 addr;
|
|
u32 reg;
|
|
|
|
addr = le16_to_cpu(ctrl->wValue);
|
|
if (addr > 127) {
|
|
dev_dbg(dwc->dev, "invalid device address %d\n", addr);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (dwc->dev_state == DWC3_CONFIGURED_STATE) {
|
|
dev_dbg(dwc->dev, "trying to set address when configured\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
|
|
reg &= ~(DWC3_DCFG_DEVADDR_MASK);
|
|
reg |= DWC3_DCFG_DEVADDR(addr);
|
|
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
|
|
|
|
if (addr)
|
|
dwc->dev_state = DWC3_ADDRESS_STATE;
|
|
else
|
|
dwc->dev_state = DWC3_DEFAULT_STATE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
|
|
{
|
|
int ret;
|
|
|
|
spin_unlock(&dwc->lock);
|
|
ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
|
|
spin_lock(&dwc->lock);
|
|
return ret;
|
|
}
|
|
|
|
static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
|
|
{
|
|
u32 cfg;
|
|
int ret;
|
|
u32 reg;
|
|
|
|
dwc->start_config_issued = false;
|
|
cfg = le16_to_cpu(ctrl->wValue);
|
|
|
|
switch (dwc->dev_state) {
|
|
case DWC3_DEFAULT_STATE:
|
|
return -EINVAL;
|
|
break;
|
|
|
|
case DWC3_ADDRESS_STATE:
|
|
ret = dwc3_ep0_delegate_req(dwc, ctrl);
|
|
/* if the cfg matches and the cfg is non zero */
|
|
if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
|
|
dwc->dev_state = DWC3_CONFIGURED_STATE;
|
|
/*
|
|
* Enable transition to U1/U2 state when
|
|
* nothing is pending from application.
|
|
*/
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
dwc->resize_fifos = true;
|
|
dev_dbg(dwc->dev, "resize fifos flag SET\n");
|
|
}
|
|
break;
|
|
|
|
case DWC3_CONFIGURED_STATE:
|
|
ret = dwc3_ep0_delegate_req(dwc, ctrl);
|
|
if (!cfg)
|
|
dwc->dev_state = DWC3_ADDRESS_STATE;
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
|
|
{
|
|
struct dwc3_ep *dep = to_dwc3_ep(ep);
|
|
struct dwc3 *dwc = dep->dwc;
|
|
|
|
u32 param = 0;
|
|
u32 reg;
|
|
|
|
struct timing {
|
|
u8 u1sel;
|
|
u8 u1pel;
|
|
u16 u2sel;
|
|
u16 u2pel;
|
|
} __packed timing;
|
|
|
|
int ret;
|
|
|
|
memcpy(&timing, req->buf, sizeof(timing));
|
|
|
|
dwc->u1sel = timing.u1sel;
|
|
dwc->u1pel = timing.u1pel;
|
|
dwc->u2sel = le16_to_cpu(timing.u2sel);
|
|
dwc->u2pel = le16_to_cpu(timing.u2pel);
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
if (reg & DWC3_DCTL_INITU2ENA)
|
|
param = dwc->u2pel;
|
|
if (reg & DWC3_DCTL_INITU1ENA)
|
|
param = dwc->u1pel;
|
|
|
|
/*
|
|
* According to Synopsys Databook, if parameter is
|
|
* greater than 125, a value of zero should be
|
|
* programmed in the register.
|
|
*/
|
|
if (param > 125)
|
|
param = 0;
|
|
|
|
/* now that we have the time, issue DGCMD Set Sel */
|
|
ret = dwc3_send_gadget_generic_command(dwc,
|
|
DWC3_DGCMD_SET_PERIODIC_PAR, param);
|
|
WARN_ON(ret < 0);
|
|
}
|
|
|
|
static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
|
|
{
|
|
struct dwc3_ep *dep;
|
|
u16 wLength;
|
|
u16 wValue;
|
|
|
|
if (dwc->dev_state == DWC3_DEFAULT_STATE)
|
|
return -EINVAL;
|
|
|
|
wValue = le16_to_cpu(ctrl->wValue);
|
|
wLength = le16_to_cpu(ctrl->wLength);
|
|
|
|
if (wLength != 6) {
|
|
dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
|
|
wLength);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* To handle Set SEL we need to receive 6 bytes from Host. So let's
|
|
* queue a usb_request for 6 bytes.
|
|
*
|
|
* Remember, though, this controller can't handle non-wMaxPacketSize
|
|
* aligned transfers on the OUT direction, so we queue a request for
|
|
* wMaxPacketSize instead.
|
|
*/
|
|
dep = dwc->eps[0];
|
|
dwc->ep0_usb_req.dep = dep;
|
|
dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
|
|
dwc->ep0_usb_req.request.buf = dwc->setup_buf;
|
|
dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
|
|
|
|
return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
|
|
}
|
|
|
|
static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
|
|
{
|
|
u16 wLength;
|
|
u16 wValue;
|
|
u16 wIndex;
|
|
|
|
wValue = le16_to_cpu(ctrl->wValue);
|
|
wLength = le16_to_cpu(ctrl->wLength);
|
|
wIndex = le16_to_cpu(ctrl->wIndex);
|
|
|
|
if (wIndex || wLength)
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* REVISIT It's unclear from Databook what to do with this
|
|
* value. For now, just cache it.
|
|
*/
|
|
dwc->isoch_delay = wValue;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
|
|
{
|
|
int ret;
|
|
|
|
switch (ctrl->bRequest) {
|
|
case USB_REQ_GET_STATUS:
|
|
dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
|
|
ret = dwc3_ep0_handle_status(dwc, ctrl);
|
|
break;
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
|
|
ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
|
|
break;
|
|
case USB_REQ_SET_FEATURE:
|
|
dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
|
|
ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
|
|
break;
|
|
case USB_REQ_SET_ADDRESS:
|
|
dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
|
|
ret = dwc3_ep0_set_address(dwc, ctrl);
|
|
break;
|
|
case USB_REQ_SET_CONFIGURATION:
|
|
dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
|
|
ret = dwc3_ep0_set_config(dwc, ctrl);
|
|
break;
|
|
case USB_REQ_SET_SEL:
|
|
dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n");
|
|
ret = dwc3_ep0_set_sel(dwc, ctrl);
|
|
break;
|
|
case USB_REQ_SET_ISOCH_DELAY:
|
|
dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
|
|
ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
|
|
break;
|
|
default:
|
|
dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
|
|
ret = dwc3_ep0_delegate_req(dwc, ctrl);
|
|
break;
|
|
};
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
|
|
const struct dwc3_event_depevt *event)
|
|
{
|
|
struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
|
|
int ret = -EINVAL;
|
|
u32 len;
|
|
|
|
if (!dwc->gadget_driver)
|
|
goto out;
|
|
|
|
len = le16_to_cpu(ctrl->wLength);
|
|
if (!len) {
|
|
dwc->three_stage_setup = false;
|
|
dwc->ep0_expect_in = false;
|
|
dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
|
|
} else {
|
|
dwc->three_stage_setup = true;
|
|
dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
|
|
dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
|
|
}
|
|
|
|
if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
|
|
ret = dwc3_ep0_std_request(dwc, ctrl);
|
|
else
|
|
ret = dwc3_ep0_delegate_req(dwc, ctrl);
|
|
|
|
if (ret == USB_GADGET_DELAYED_STATUS)
|
|
dwc->delayed_status = true;
|
|
|
|
out:
|
|
if (ret < 0)
|
|
dwc3_ep0_stall_and_restart(dwc);
|
|
}
|
|
|
|
static void dwc3_ep0_complete_data(struct dwc3 *dwc,
|
|
const struct dwc3_event_depevt *event)
|
|
{
|
|
struct dwc3_request *r = NULL;
|
|
struct usb_request *ur;
|
|
struct dwc3_trb *trb;
|
|
struct dwc3_ep *ep0;
|
|
u32 transferred;
|
|
u32 status;
|
|
u32 length;
|
|
u8 epnum;
|
|
|
|
epnum = event->endpoint_number;
|
|
ep0 = dwc->eps[0];
|
|
|
|
dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
|
|
|
|
r = next_request(&ep0->request_list);
|
|
ur = &r->request;
|
|
|
|
trb = dwc->ep0_trb;
|
|
|
|
status = DWC3_TRB_SIZE_TRBSTS(trb->size);
|
|
if (status == DWC3_TRBSTS_SETUP_PENDING) {
|
|
dev_dbg(dwc->dev, "Setup Pending received\n");
|
|
|
|
if (r)
|
|
dwc3_gadget_giveback(ep0, r, -ECONNRESET);
|
|
|
|
return;
|
|
}
|
|
|
|
length = trb->size & DWC3_TRB_SIZE_MASK;
|
|
|
|
if (dwc->ep0_bounced) {
|
|
unsigned transfer_size = ur->length;
|
|
unsigned maxp = ep0->endpoint.maxpacket;
|
|
|
|
transfer_size += (maxp - (transfer_size % maxp));
|
|
transferred = min_t(u32, ur->length,
|
|
transfer_size - length);
|
|
memcpy(ur->buf, dwc->ep0_bounce, transferred);
|
|
} else {
|
|
transferred = ur->length - length;
|
|
}
|
|
|
|
ur->actual += transferred;
|
|
|
|
if ((epnum & 1) && ur->actual < ur->length) {
|
|
/* for some reason we did not get everything out */
|
|
|
|
dwc3_ep0_stall_and_restart(dwc);
|
|
} else {
|
|
/*
|
|
* handle the case where we have to send a zero packet. This
|
|
* seems to be case when req.length > maxpacket. Could it be?
|
|
*/
|
|
if (r)
|
|
dwc3_gadget_giveback(ep0, r, 0);
|
|
}
|
|
}
|
|
|
|
static void dwc3_ep0_complete_status(struct dwc3 *dwc,
|
|
const struct dwc3_event_depevt *event)
|
|
{
|
|
struct dwc3_request *r;
|
|
struct dwc3_ep *dep;
|
|
struct dwc3_trb *trb;
|
|
u32 status;
|
|
|
|
dep = dwc->eps[0];
|
|
trb = dwc->ep0_trb;
|
|
|
|
if (!list_empty(&dep->request_list)) {
|
|
r = next_request(&dep->request_list);
|
|
|
|
dwc3_gadget_giveback(dep, r, 0);
|
|
}
|
|
|
|
if (dwc->test_mode) {
|
|
int ret;
|
|
|
|
ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
|
|
if (ret < 0) {
|
|
dev_dbg(dwc->dev, "Invalid Test #%d\n",
|
|
dwc->test_mode_nr);
|
|
dwc3_ep0_stall_and_restart(dwc);
|
|
return;
|
|
}
|
|
}
|
|
|
|
status = DWC3_TRB_SIZE_TRBSTS(trb->size);
|
|
if (status == DWC3_TRBSTS_SETUP_PENDING)
|
|
dev_dbg(dwc->dev, "Setup Pending received\n");
|
|
|
|
dwc->ep0state = EP0_SETUP_PHASE;
|
|
dwc3_ep0_out_start(dwc);
|
|
}
|
|
|
|
static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
|
|
const struct dwc3_event_depevt *event)
|
|
{
|
|
struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
|
|
|
|
dep->flags &= ~DWC3_EP_BUSY;
|
|
dep->resource_index = 0;
|
|
dwc->setup_packet_pending = false;
|
|
|
|
switch (dwc->ep0state) {
|
|
case EP0_SETUP_PHASE:
|
|
dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
|
|
dwc3_ep0_inspect_setup(dwc, event);
|
|
break;
|
|
|
|
case EP0_DATA_PHASE:
|
|
dev_vdbg(dwc->dev, "Data Phase\n");
|
|
dwc3_ep0_complete_data(dwc, event);
|
|
break;
|
|
|
|
case EP0_STATUS_PHASE:
|
|
dev_vdbg(dwc->dev, "Status Phase\n");
|
|
dwc3_ep0_complete_status(dwc, event);
|
|
break;
|
|
default:
|
|
WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
|
|
}
|
|
}
|
|
|
|
static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
|
|
struct dwc3_ep *dep, struct dwc3_request *req)
|
|
{
|
|
int ret;
|
|
|
|
req->direction = !!dep->number;
|
|
|
|
if (req->request.length == 0) {
|
|
ret = dwc3_ep0_start_trans(dwc, dep->number,
|
|
dwc->ctrl_req_addr, 0,
|
|
DWC3_TRBCTL_CONTROL_DATA);
|
|
} else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
|
|
&& (dep->number == 0)) {
|
|
u32 transfer_size;
|
|
u32 maxpacket;
|
|
|
|
ret = usb_gadget_map_request(&dwc->gadget, &req->request,
|
|
dep->number);
|
|
if (ret) {
|
|
dev_dbg(dwc->dev, "failed to map request\n");
|
|
return;
|
|
}
|
|
|
|
WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
|
|
|
|
maxpacket = dep->endpoint.maxpacket;
|
|
transfer_size = roundup(req->request.length, maxpacket);
|
|
|
|
dwc->ep0_bounced = true;
|
|
|
|
/*
|
|
* REVISIT in case request length is bigger than
|
|
* DWC3_EP0_BOUNCE_SIZE we will need two chained
|
|
* TRBs to handle the transfer.
|
|
*/
|
|
ret = dwc3_ep0_start_trans(dwc, dep->number,
|
|
dwc->ep0_bounce_addr, transfer_size,
|
|
DWC3_TRBCTL_CONTROL_DATA);
|
|
} else {
|
|
ret = usb_gadget_map_request(&dwc->gadget, &req->request,
|
|
dep->number);
|
|
if (ret) {
|
|
dev_dbg(dwc->dev, "failed to map request\n");
|
|
return;
|
|
}
|
|
|
|
ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
|
|
req->request.length, DWC3_TRBCTL_CONTROL_DATA);
|
|
}
|
|
|
|
WARN_ON(ret < 0);
|
|
}
|
|
|
|
static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
|
|
{
|
|
struct dwc3 *dwc = dep->dwc;
|
|
u32 type;
|
|
|
|
type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
|
|
: DWC3_TRBCTL_CONTROL_STATUS2;
|
|
|
|
return dwc3_ep0_start_trans(dwc, dep->number,
|
|
dwc->ctrl_req_addr, 0, type);
|
|
}
|
|
|
|
static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
|
|
{
|
|
if (dwc->resize_fifos) {
|
|
dev_dbg(dwc->dev, "starting to resize fifos\n");
|
|
dwc3_gadget_resize_tx_fifos(dwc);
|
|
dwc->resize_fifos = 0;
|
|
}
|
|
|
|
WARN_ON(dwc3_ep0_start_control_status(dep));
|
|
}
|
|
|
|
static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
|
|
const struct dwc3_event_depevt *event)
|
|
{
|
|
struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
|
|
|
|
__dwc3_ep0_do_control_status(dwc, dep);
|
|
}
|
|
|
|
static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
|
|
{
|
|
struct dwc3_gadget_ep_cmd_params params;
|
|
u32 cmd;
|
|
int ret;
|
|
|
|
if (!dep->resource_index)
|
|
return;
|
|
|
|
cmd = DWC3_DEPCMD_ENDTRANSFER;
|
|
cmd |= DWC3_DEPCMD_CMDIOC;
|
|
cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
|
|
memset(¶ms, 0, sizeof(params));
|
|
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
|
|
WARN_ON_ONCE(ret);
|
|
dep->resource_index = 0;
|
|
}
|
|
|
|
static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
|
|
const struct dwc3_event_depevt *event)
|
|
{
|
|
dwc->setup_packet_pending = true;
|
|
|
|
switch (event->status) {
|
|
case DEPEVT_STATUS_CONTROL_DATA:
|
|
dev_vdbg(dwc->dev, "Control Data\n");
|
|
|
|
/*
|
|
* We already have a DATA transfer in the controller's cache,
|
|
* if we receive a XferNotReady(DATA) we will ignore it, unless
|
|
* it's for the wrong direction.
|
|
*
|
|
* In that case, we must issue END_TRANSFER command to the Data
|
|
* Phase we already have started and issue SetStall on the
|
|
* control endpoint.
|
|
*/
|
|
if (dwc->ep0_expect_in != event->endpoint_number) {
|
|
struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
|
|
|
|
dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
|
|
dwc3_ep0_end_control_data(dwc, dep);
|
|
dwc3_ep0_stall_and_restart(dwc);
|
|
return;
|
|
}
|
|
|
|
break;
|
|
|
|
case DEPEVT_STATUS_CONTROL_STATUS:
|
|
if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
|
|
return;
|
|
|
|
dev_vdbg(dwc->dev, "Control Status\n");
|
|
|
|
dwc->ep0state = EP0_STATUS_PHASE;
|
|
|
|
if (dwc->delayed_status) {
|
|
WARN_ON_ONCE(event->endpoint_number != 1);
|
|
dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
|
|
return;
|
|
}
|
|
|
|
dwc3_ep0_do_control_status(dwc, event);
|
|
}
|
|
}
|
|
|
|
void dwc3_ep0_interrupt(struct dwc3 *dwc,
|
|
const struct dwc3_event_depevt *event)
|
|
{
|
|
u8 epnum = event->endpoint_number;
|
|
|
|
dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
|
|
dwc3_ep_event_string(event->endpoint_event),
|
|
epnum >> 1, (epnum & 1) ? "in" : "out",
|
|
dwc3_ep0_state_string(dwc->ep0state));
|
|
|
|
switch (event->endpoint_event) {
|
|
case DWC3_DEPEVT_XFERCOMPLETE:
|
|
dwc3_ep0_xfer_complete(dwc, event);
|
|
break;
|
|
|
|
case DWC3_DEPEVT_XFERNOTREADY:
|
|
dwc3_ep0_xfernotready(dwc, event);
|
|
break;
|
|
|
|
case DWC3_DEPEVT_XFERINPROGRESS:
|
|
case DWC3_DEPEVT_RXTXFIFOEVT:
|
|
case DWC3_DEPEVT_STREAMEVT:
|
|
case DWC3_DEPEVT_EPCMDCMPLT:
|
|
break;
|
|
}
|
|
}
|