AuxXxilium/linux_dsm_epyc7002
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0813c40556
linux_dsm_epyc7002/arch/x86/events
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Kan Liang 0813c40556 perf/x86/intel: Add more available bits for OFFCORE_RESPONSE of Intel Tremont 
The mask in the extra_regs for Intel Tremont need to be extended to
allow more defined bits.

"Outstanding Requests" (bit 63) is only available on MSR_OFFCORE_RSP0;

Fixes: 6daeb8737f ("perf/x86/intel: Add Tremont core PMU support")
Reported-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20200501125442.7030-1-kan.liang@linux.intel.com
2020-05-19 20:34:16 +02:00
..
amd Merge branch 'x86/cpu' into perf/core, to resolve conflict 2020-03-25 15:20:44 +01:00
intel perf/x86/intel: Add more available bits for OFFCORE_RESPONSE of Intel Tremont 2020-05-19 20:34:16 +02:00
zhaoxin x86/perf: Add hardware performance events support for Zhaoxin CPU. 2020-04-30 20:14:35 +02:00
core.c x86/perf: Add hardware performance events support for Zhaoxin CPU. 2020-04-30 20:14:35 +02:00
Kconfig License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
Makefile x86/perf: Add hardware performance events support for Zhaoxin CPU. 2020-04-30 20:14:35 +02:00
msr.c perf/x86/msr: Add Tremont support 2020-02-11 13:17:50 +01:00
perf_event.h x86/perf: Add hardware performance events support for Zhaoxin CPU. 2020-04-30 20:14:35 +02:00
probe.c perf/x86: Add MSR probe interface 2019-06-24 19:28:31 +02:00
probe.h perf/x86: Add MSR probe interface 2019-06-24 19:28:31 +02:00