mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 09:55:29 +07:00
4e903450bc
gcc-8 reports an uninitialized variable access in a code path
that we would see with incorrect DTB input:
drivers/clk/sunxi/clk-sun8i-bus-gates.c: In function 'sun8i_h3_bus_gates_init':
drivers/clk/sunxi/clk-sun8i-bus-gates.c:85:27: error: 'clk_parent' may be used uninitialized in this function [-Werror=maybe-uninitialized]
This works around by skipping invalid input and printing a warning
instead if it ever happens. The problem was apparently part of the
initiali driver submission, but older compilers don't notice it.
Fixes: ab6e23a4e3 ("clk: sunxi: Add H3 clocks support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
118 lines
3.1 KiB
C
118 lines
3.1 KiB
C
/*
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* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
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*
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* Based on clk-simple-gates.c, which is:
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* Copyright 2015 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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static DEFINE_SPINLOCK(gates_lock);
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static void __init sun8i_h3_bus_gates_init(struct device_node *node)
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{
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static const char * const names[] = { "ahb1", "ahb2", "apb1", "apb2" };
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enum { AHB1, AHB2, APB1, APB2, PARENT_MAX } clk_parent;
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const char *parents[PARENT_MAX];
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struct clk_onecell_data *clk_data;
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const char *clk_name;
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struct property *prop;
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struct resource res;
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void __iomem *clk_reg;
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void __iomem *reg;
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const __be32 *p;
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int number, i;
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u8 clk_bit;
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int index;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (IS_ERR(reg))
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return;
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for (i = 0; i < ARRAY_SIZE(names); i++) {
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int idx = of_property_match_string(node, "clock-names",
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names[i]);
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if (idx < 0)
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return;
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parents[i] = of_clk_get_parent_name(node, idx);
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}
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clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
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if (!clk_data)
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goto err_unmap;
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number = of_property_count_u32_elems(node, "clock-indices");
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of_property_read_u32_index(node, "clock-indices", number - 1, &number);
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clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
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if (!clk_data->clks)
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goto err_free_data;
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i = 0;
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of_property_for_each_u32(node, "clock-indices", prop, p, index) {
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of_property_read_string_index(node, "clock-output-names",
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i, &clk_name);
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if (index == 17 || (index >= 29 && index <= 31))
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clk_parent = AHB2;
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else if (index <= 63 || index >= 128)
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clk_parent = AHB1;
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else if (index >= 64 && index <= 95)
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clk_parent = APB1;
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else if (index >= 96 && index <= 127)
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clk_parent = APB2;
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else {
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WARN_ON(true);
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continue;
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}
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clk_reg = reg + 4 * (index / 32);
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clk_bit = index % 32;
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clk_data->clks[index] = clk_register_gate(NULL, clk_name,
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parents[clk_parent],
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0, clk_reg, clk_bit,
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0, &gates_lock);
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i++;
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if (IS_ERR(clk_data->clks[index])) {
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WARN_ON(true);
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continue;
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}
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}
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clk_data->clk_num = number + 1;
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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return;
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err_free_data:
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kfree(clk_data);
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err_unmap:
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iounmap(reg);
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of_address_to_resource(node, 0, &res);
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release_mem_region(res.start, resource_size(&res));
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}
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CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk",
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sun8i_h3_bus_gates_init);
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CLK_OF_DECLARE(sun8i_a83t_bus_gates, "allwinner,sun8i-a83t-bus-gates-clk",
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sun8i_h3_bus_gates_init);
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