Anthony Koo 07d6a19921 drm/amd/display: Fix soft hang issue when some DPCD data invalid ... [Why] AUX transaction returns success, but data has invalid lane count and rate which when passed to VBIOS command table causes it to soft hang [How] Do some sanity checking and fail if the DPCD caps are invalid. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-03-19 15:04:03 -05:00
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drm	drm/amd/display: Fix soft hang issue when some DPCD data invalid	2019-03-19 15:04:03 -05:00
host1x	gpu: host1x: Continue CDMA execution starting with a next job	2019-02-07 18:34:25 +01:00
ipu-v3	gpu: ipu-v3: pre: don't trigger update if buffer address doesn't change	2019-01-23 11:56:44 +01:00
vga	vga-switcheroo: make PCI dependency explicit	2019-01-15 23:16:47 +01:00
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