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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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5184d44960
- Clean up reset gpio handler - Defconfig updates - Add support for 8 byte get_user() - Switch to generic dma code In merge please fix dma_atomic_pool_init reported also by: https://lkml.org/lkml/2019/9/2/393 or https://lore.kernel.org/linux-next/20190902214011.2a5400c9@canb.auug.org.au/ -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCXYnguwAKCRDKSWXLKUoM IaF8AKCawdYH+58xRg7riR7Evbv2kM0ghwCfXosnu6Ncv07UEY9Tv5zx/qibafk= =yI3X -----END PGP SIGNATURE----- Merge tag 'microblaze-v5.4-rc1' of git://git.monstr.eu/linux-2.6-microblaze Pull Microblaze updates from Michal Simek: - clean up reset gpio handler - defconfig updates - add support for 8 byte get_user() - switch to generic dma code * tag 'microblaze-v5.4-rc1' of git://git.monstr.eu/linux-2.6-microblaze: microblaze: Switch to standard restart handler microblaze: defconfig synchronization microblaze: Enable Xilinx AXI emac driver by default arch/microblaze: support get_user() of size 8 bytes microblaze: remove ioremap_fullcache microblaze: use the generic dma coherent remap allocator microblaze/nommu: use the generic uncached segment support
60 lines
1.8 KiB
C
60 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Microblaze support for cache consistent memory.
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* Copyright (C) 2010 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2010 PetaLogix
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* Copyright (C) 2005 John Williams <jwilliams@itee.uq.edu.au>
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*/
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/dma-noncoherent.h>
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#include <asm/cpuinfo.h>
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#include <asm/cacheflush.h>
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void arch_dma_prep_coherent(struct page *page, size_t size)
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{
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phys_addr_t paddr = page_to_phys(page);
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flush_dcache_range(paddr, paddr + size);
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}
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#ifndef CONFIG_MMU
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/*
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* Consistent memory allocators. Used for DMA devices that want to share
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* uncached memory with the processor core. My crufty no-MMU approach is
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* simple. In the HW platform we can optionally mirror the DDR up above the
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* processor cacheable region. So, memory accessed in this mirror region will
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* not be cached. It's alloced from the same pool as normal memory, but the
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* handle we return is shifted up into the uncached region. This will no doubt
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* cause big problems if memory allocated here is not also freed properly. -- JW
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*
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* I have to use dcache values because I can't relate on ram size:
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*/
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#ifdef CONFIG_XILINX_UNCACHED_SHADOW
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#define UNCACHED_SHADOW_MASK (cpuinfo.dcache_high - cpuinfo.dcache_base + 1)
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#else
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#define UNCACHED_SHADOW_MASK 0
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#endif /* CONFIG_XILINX_UNCACHED_SHADOW */
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void *uncached_kernel_address(void *ptr)
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{
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unsigned long addr = (unsigned long)ptr;
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addr |= UNCACHED_SHADOW_MASK;
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if (addr > cpuinfo.dcache_base && addr < cpuinfo.dcache_high)
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pr_warn("ERROR: Your cache coherent area is CACHED!!!\n");
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return (void *)addr;
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}
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void *cached_kernel_address(void *ptr)
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{
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unsigned long addr = (unsigned long)ptr;
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return (void *)(addr & ~UNCACHED_SHADOW_MASK);
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}
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#endif /* CONFIG_MMU */
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