mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 06:50:55 +07:00
a753499d43
MMU contains invalid mapping which wasn't flushed and new mapping is using the same addresses as previous one. That's why TLB miss is not happening to get new correct TLB entry and MMU points to incorrect area. This is replicatable when large files(256MB and more) are copied and checked. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
||
---|---|---|
.. | ||
consistent.c | ||
fault.c | ||
highmem.c | ||
init.c | ||
Makefile | ||
mmu_context.c | ||
pgtable.c |