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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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0762097625
The background operations of the L2x0 cache controllers are aborted if another operation is issued on the same or different core. This patch protects the maintenance operation issuing/polling with a spinlock. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
/*
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* arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
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*
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* Copyright (C) 2007 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <asm/cacheflush.h>
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#include <asm/io.h>
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#include <asm/hardware/cache-l2x0.h>
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#define CACHE_LINE_SIZE 32
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static void __iomem *l2x0_base;
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static DEFINE_SPINLOCK(l2x0_lock);
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static inline void sync_writel(unsigned long val, unsigned long reg,
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unsigned long complete_mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&l2x0_lock, flags);
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writel(val, l2x0_base + reg);
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/* wait for the operation to complete */
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while (readl(l2x0_base + reg) & complete_mask)
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;
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static inline void cache_sync(void)
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{
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sync_writel(0, L2X0_CACHE_SYNC, 1);
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}
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static inline void l2x0_inv_all(void)
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{
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/* invalidate all ways */
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sync_writel(0xff, L2X0_INV_WAY, 0xff);
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cache_sync();
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}
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static void l2x0_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long addr;
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start &= ~(CACHE_LINE_SIZE - 1);
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for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
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sync_writel(addr, L2X0_INV_LINE_PA, 1);
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cache_sync();
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}
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static void l2x0_clean_range(unsigned long start, unsigned long end)
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{
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unsigned long addr;
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start &= ~(CACHE_LINE_SIZE - 1);
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for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
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sync_writel(addr, L2X0_CLEAN_LINE_PA, 1);
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cache_sync();
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}
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static void l2x0_flush_range(unsigned long start, unsigned long end)
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{
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unsigned long addr;
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start &= ~(CACHE_LINE_SIZE - 1);
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for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
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sync_writel(addr, L2X0_CLEAN_INV_LINE_PA, 1);
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cache_sync();
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}
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void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
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{
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__u32 aux;
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l2x0_base = base;
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/* disable L2X0 */
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writel(0, l2x0_base + L2X0_CTRL);
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aux = readl(l2x0_base + L2X0_AUX_CTRL);
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aux &= aux_mask;
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aux |= aux_val;
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writel(aux, l2x0_base + L2X0_AUX_CTRL);
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l2x0_inv_all();
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/* enable L2X0 */
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writel(1, l2x0_base + L2X0_CTRL);
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outer_cache.inv_range = l2x0_inv_range;
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outer_cache.clean_range = l2x0_clean_range;
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outer_cache.flush_range = l2x0_flush_range;
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printk(KERN_INFO "L2X0 cache controller enabled\n");
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}
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