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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1839 lines
47 KiB
C
1839 lines
47 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Hardware modules present on the OMAP44xx chips
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*
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* Copyright (C) 2009-2012 Texas Instruments, Inc.
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* Copyright (C) 2009-2010 Nokia Corporation
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*
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* Paul Walmsley
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* Benoit Cousson
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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* Note that this file is currently not in sync with autogeneration scripts.
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* The above note to be removed, once it is synced up.
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*/
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#include <linux/io.h>
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#include "omap_hwmod.h"
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#include "omap_hwmod_common_data.h"
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#include "cm1_44xx.h"
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#include "cm2_44xx.h"
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#include "prm44xx.h"
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#include "prm-regbits-44xx.h"
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/* Base offset for all OMAP4 interrupts external to MPUSS */
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#define OMAP44XX_IRQ_GIC_START 32
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/*
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* IP blocks
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*/
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/*
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* 'dmm' class
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* instance(s): dmm
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*/
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static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
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.name = "dmm",
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};
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/* dmm */
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static struct omap_hwmod omap44xx_dmm_hwmod = {
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.name = "dmm",
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.class = &omap44xx_dmm_hwmod_class,
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.clkdm_name = "l3_emif_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
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},
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},
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};
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/*
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* 'l3' class
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* instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
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*/
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static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
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.name = "l3",
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};
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/* l3_instr */
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static struct omap_hwmod omap44xx_l3_instr_hwmod = {
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.name = "l3_instr",
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.class = &omap44xx_l3_hwmod_class,
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.clkdm_name = "l3_instr_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/* l3_main_1 */
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static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
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.name = "l3_main_1",
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.class = &omap44xx_l3_hwmod_class,
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.clkdm_name = "l3_1_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
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},
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},
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};
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/* l3_main_2 */
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static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
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.name = "l3_main_2",
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.class = &omap44xx_l3_hwmod_class,
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.clkdm_name = "l3_2_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
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},
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},
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};
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/* l3_main_3 */
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static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
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.name = "l3_main_3",
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.class = &omap44xx_l3_hwmod_class,
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.clkdm_name = "l3_instr_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/*
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* 'l4' class
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* instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
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*/
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static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
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.name = "l4",
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};
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/* l4_abe */
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static struct omap_hwmod omap44xx_l4_abe_hwmod = {
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.name = "l4_abe",
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.class = &omap44xx_l4_hwmod_class,
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.clkdm_name = "abe_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
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.lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
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},
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},
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};
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/* l4_cfg */
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static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
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.name = "l4_cfg",
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.class = &omap44xx_l4_hwmod_class,
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.clkdm_name = "l4_cfg_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
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},
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},
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};
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/* l4_per */
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static struct omap_hwmod omap44xx_l4_per_hwmod = {
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.name = "l4_per",
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.class = &omap44xx_l4_hwmod_class,
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.clkdm_name = "l4_per_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
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},
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},
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};
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/* l4_wkup */
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static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
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.name = "l4_wkup",
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.class = &omap44xx_l4_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
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},
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},
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};
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/*
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* 'mpu_bus' class
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* instance(s): mpu_private
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*/
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static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
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.name = "mpu_bus",
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};
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/* mpu_private */
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static struct omap_hwmod omap44xx_mpu_private_hwmod = {
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.name = "mpu_private",
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.class = &omap44xx_mpu_bus_hwmod_class,
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.clkdm_name = "mpuss_clkdm",
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.prcm = {
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.omap4 = {
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
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},
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},
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};
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/*
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* 'ocp_wp_noc' class
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* instance(s): ocp_wp_noc
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*/
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static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
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.name = "ocp_wp_noc",
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};
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/* ocp_wp_noc */
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static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
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.name = "ocp_wp_noc",
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.class = &omap44xx_ocp_wp_noc_hwmod_class,
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.clkdm_name = "l3_instr_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/*
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* Modules omap_hwmod structures
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*
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* The following IPs are excluded for the moment because:
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* - They do not need an explicit SW control using omap_hwmod API.
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* - They still need to be validated with the driver
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* properly adapted to omap_hwmod / omap_device
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*
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* usim
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*/
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/*
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* 'counter' class
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* 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
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*/
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static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0004,
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.sysc_flags = SYSC_HAS_SIDLEMODE,
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.idlemodes = (SIDLE_FORCE | SIDLE_NO),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
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.name = "counter",
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.sysc = &omap44xx_counter_sysc,
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};
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/* counter_32k */
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static struct omap_hwmod omap44xx_counter_32k_hwmod = {
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.name = "counter_32k",
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.class = &omap44xx_counter_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.flags = HWMOD_SWSUP_SIDLE,
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.main_clk = "sys_32k_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
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},
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},
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};
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/*
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* 'ctrl_module' class
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* attila core control module + core pad control module + wkup pad control
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* module + attila wkup control module
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*/
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static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.sysc_flags = SYSC_HAS_SIDLEMODE,
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type2,
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};
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static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
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.name = "ctrl_module",
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.sysc = &omap44xx_ctrl_module_sysc,
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};
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/* ctrl_module_core */
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static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
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.name = "ctrl_module_core",
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.class = &omap44xx_ctrl_module_hwmod_class,
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.clkdm_name = "l4_cfg_clkdm",
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.prcm = {
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.omap4 = {
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
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},
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},
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};
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/* ctrl_module_pad_core */
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static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
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.name = "ctrl_module_pad_core",
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.class = &omap44xx_ctrl_module_hwmod_class,
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.clkdm_name = "l4_cfg_clkdm",
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.prcm = {
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.omap4 = {
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
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},
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},
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};
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/* ctrl_module_wkup */
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static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
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.name = "ctrl_module_wkup",
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.class = &omap44xx_ctrl_module_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.prcm = {
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.omap4 = {
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
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},
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},
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};
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/* ctrl_module_pad_wkup */
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static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
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.name = "ctrl_module_pad_wkup",
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.class = &omap44xx_ctrl_module_hwmod_class,
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.clkdm_name = "l4_wkup_clkdm",
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.prcm = {
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.omap4 = {
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
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},
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},
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};
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/*
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* 'debugss' class
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* debug and emulation sub system
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*/
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static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
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.name = "debugss",
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};
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/* debugss */
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static struct omap_hwmod omap44xx_debugss_hwmod = {
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.name = "debugss",
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.class = &omap44xx_debugss_hwmod_class,
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.clkdm_name = "emu_sys_clkdm",
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.main_clk = "trace_clk_div_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
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},
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},
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};
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/*
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* 'dsp' class
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* dsp sub-system
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*/
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static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
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.name = "dsp",
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};
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/* dsp */
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static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
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{ .name = "dsp", .rst_shift = 0 },
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};
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static struct omap_hwmod omap44xx_dsp_hwmod = {
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.name = "dsp",
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.class = &omap44xx_dsp_hwmod_class,
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.clkdm_name = "tesla_clkdm",
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.rst_lines = omap44xx_dsp_resets,
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.rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
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.main_clk = "dpll_iva_m4x2_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
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.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
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.context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/*
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* 'dss' class
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* display sub-system
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*/
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static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
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.rev_offs = 0x0000,
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.syss_offs = 0x0014,
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.sysc_flags = SYSS_HAS_RESET_STATUS,
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};
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static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
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.name = "dss",
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.sysc = &omap44xx_dss_sysc,
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.reset = omap_dss_reset,
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};
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/* dss */
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static struct omap_hwmod_opt_clk dss_opt_clks[] = {
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{ .role = "sys_clk", .clk = "dss_sys_clk" },
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{ .role = "tv_clk", .clk = "dss_tv_clk" },
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{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
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};
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static struct omap_hwmod omap44xx_dss_hwmod = {
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.name = "dss_core",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.class = &omap44xx_dss_hwmod_class,
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.clkdm_name = "l3_dss_clkdm",
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.main_clk = "dss_dss_clk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
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.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.opt_clks = dss_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
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};
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/*
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* 'dispc' class
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* display controller
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*/
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static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
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SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
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SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
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.name = "dispc",
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.sysc = &omap44xx_dispc_sysc,
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};
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/* dss_dispc */
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static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
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.manager_count = 3,
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.has_framedonetv_irq = 1
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};
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static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
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.name = "dss_dispc",
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.class = &omap44xx_dispc_hwmod_class,
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.clkdm_name = "l3_dss_clkdm",
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.main_clk = "dss_dss_clk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
|
|
},
|
|
},
|
|
.dev_attr = &omap44xx_dss_dispc_dev_attr,
|
|
.parent_hwmod = &omap44xx_dss_hwmod,
|
|
};
|
|
|
|
/*
|
|
* 'dsi' class
|
|
* display serial interface controller
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
|
|
.name = "dsi",
|
|
.sysc = &omap44xx_dsi_sysc,
|
|
};
|
|
|
|
/* dss_dsi1 */
|
|
static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
|
|
{ .role = "sys_clk", .clk = "dss_sys_clk" },
|
|
};
|
|
|
|
static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
|
|
.name = "dss_dsi1",
|
|
.class = &omap44xx_dsi_hwmod_class,
|
|
.clkdm_name = "l3_dss_clkdm",
|
|
.main_clk = "dss_dss_clk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
|
|
},
|
|
},
|
|
.opt_clks = dss_dsi1_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
|
|
.parent_hwmod = &omap44xx_dss_hwmod,
|
|
};
|
|
|
|
/* dss_dsi2 */
|
|
static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
|
|
{ .role = "sys_clk", .clk = "dss_sys_clk" },
|
|
};
|
|
|
|
static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
|
|
.name = "dss_dsi2",
|
|
.class = &omap44xx_dsi_hwmod_class,
|
|
.clkdm_name = "l3_dss_clkdm",
|
|
.main_clk = "dss_dss_clk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
|
|
},
|
|
},
|
|
.opt_clks = dss_dsi2_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
|
|
.parent_hwmod = &omap44xx_dss_hwmod,
|
|
};
|
|
|
|
/*
|
|
* 'hdmi' class
|
|
* hdmi controller
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
|
|
.name = "hdmi",
|
|
.sysc = &omap44xx_hdmi_sysc,
|
|
};
|
|
|
|
/* dss_hdmi */
|
|
static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
|
|
{ .role = "sys_clk", .clk = "dss_sys_clk" },
|
|
{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
|
|
};
|
|
|
|
static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
|
|
.name = "dss_hdmi",
|
|
.class = &omap44xx_hdmi_hwmod_class,
|
|
.clkdm_name = "l3_dss_clkdm",
|
|
/*
|
|
* HDMI audio requires to use no-idle mode. Hence,
|
|
* set idle mode by software.
|
|
*/
|
|
.flags = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
|
|
.main_clk = "dss_48mhz_clk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
|
|
},
|
|
},
|
|
.opt_clks = dss_hdmi_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
|
|
.parent_hwmod = &omap44xx_dss_hwmod,
|
|
};
|
|
|
|
/*
|
|
* 'rfbi' class
|
|
* remote frame buffer interface
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
|
|
.name = "rfbi",
|
|
.sysc = &omap44xx_rfbi_sysc,
|
|
};
|
|
|
|
/* dss_rfbi */
|
|
static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
|
|
{ .role = "ick", .clk = "l3_div_ck" },
|
|
};
|
|
|
|
static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
|
|
.name = "dss_rfbi",
|
|
.class = &omap44xx_rfbi_hwmod_class,
|
|
.clkdm_name = "l3_dss_clkdm",
|
|
.main_clk = "dss_dss_clk",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
|
|
},
|
|
},
|
|
.opt_clks = dss_rfbi_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
|
|
.parent_hwmod = &omap44xx_dss_hwmod,
|
|
};
|
|
|
|
/*
|
|
* 'venc' class
|
|
* video encoder
|
|
*/
|
|
|
|
static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
|
|
.name = "venc",
|
|
};
|
|
|
|
/* dss_venc */
|
|
static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
|
|
{ .role = "tv_clk", .clk = "dss_tv_clk" },
|
|
};
|
|
|
|
static struct omap_hwmod omap44xx_dss_venc_hwmod = {
|
|
.name = "dss_venc",
|
|
.class = &omap44xx_venc_hwmod_class,
|
|
.clkdm_name = "l3_dss_clkdm",
|
|
.main_clk = "dss_tv_clk",
|
|
.flags = HWMOD_OPT_CLKS_NEEDED,
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
|
|
},
|
|
},
|
|
.parent_hwmod = &omap44xx_dss_hwmod,
|
|
.opt_clks = dss_venc_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
* 'emif' class
|
|
* external memory interface no1
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
|
|
.rev_offs = 0x0000,
|
|
};
|
|
|
|
static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
|
|
.name = "emif",
|
|
.sysc = &omap44xx_emif_sysc,
|
|
};
|
|
|
|
/* emif1 */
|
|
static struct omap_hwmod omap44xx_emif1_hwmod = {
|
|
.name = "emif1",
|
|
.class = &omap44xx_emif_hwmod_class,
|
|
.clkdm_name = "l3_emif_clkdm",
|
|
.flags = HWMOD_INIT_NO_IDLE,
|
|
.main_clk = "ddrphy_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* emif2 */
|
|
static struct omap_hwmod omap44xx_emif2_hwmod = {
|
|
.name = "emif2",
|
|
.class = &omap44xx_emif_hwmod_class,
|
|
.clkdm_name = "l3_emif_clkdm",
|
|
.flags = HWMOD_INIT_NO_IDLE,
|
|
.main_clk = "ddrphy_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'gpmc' class
|
|
* general purpose memory controller
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
|
|
.name = "gpmc",
|
|
.sysc = &omap44xx_gpmc_sysc,
|
|
};
|
|
|
|
/* gpmc */
|
|
static struct omap_hwmod omap44xx_gpmc_hwmod = {
|
|
.name = "gpmc",
|
|
.class = &omap44xx_gpmc_hwmod_class,
|
|
.clkdm_name = "l3_2_clkdm",
|
|
/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
|
|
.flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
|
|
/*
|
|
* 'ipu' class
|
|
* imaging processor unit
|
|
*/
|
|
|
|
static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
|
|
.name = "ipu",
|
|
};
|
|
|
|
/* ipu */
|
|
static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
|
|
{ .name = "cpu0", .rst_shift = 0 },
|
|
{ .name = "cpu1", .rst_shift = 1 },
|
|
};
|
|
|
|
static struct omap_hwmod omap44xx_ipu_hwmod = {
|
|
.name = "ipu",
|
|
.class = &omap44xx_ipu_hwmod_class,
|
|
.clkdm_name = "ducati_clkdm",
|
|
.rst_lines = omap44xx_ipu_resets,
|
|
.rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
|
|
.main_clk = "ducati_clk_mux_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
|
|
.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'iss' class
|
|
* external images sensor pixel data processor
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
/*
|
|
* ISS needs 100 OCP clk cycles delay after a softreset before
|
|
* accessing sysconfig again.
|
|
* The lowest frequency at the moment for L3 bus is 100 MHz, so
|
|
* 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
|
|
*
|
|
* TODO: Indicate errata when available.
|
|
*/
|
|
.srst_udelay = 2,
|
|
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
|
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
|
|
.name = "iss",
|
|
.sysc = &omap44xx_iss_sysc,
|
|
};
|
|
|
|
/* iss */
|
|
static struct omap_hwmod_opt_clk iss_opt_clks[] = {
|
|
{ .role = "ctrlclk", .clk = "iss_ctrlclk" },
|
|
};
|
|
|
|
static struct omap_hwmod omap44xx_iss_hwmod = {
|
|
.name = "iss",
|
|
.class = &omap44xx_iss_hwmod_class,
|
|
.clkdm_name = "iss_clkdm",
|
|
.main_clk = "ducati_clk_mux_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
.opt_clks = iss_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
|
|
};
|
|
|
|
/*
|
|
* 'iva' class
|
|
* multi-standard video encoder/decoder hardware accelerator
|
|
*/
|
|
|
|
static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
|
|
.name = "iva",
|
|
};
|
|
|
|
/* iva */
|
|
static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
|
|
{ .name = "seq0", .rst_shift = 0 },
|
|
{ .name = "seq1", .rst_shift = 1 },
|
|
{ .name = "logic", .rst_shift = 2 },
|
|
};
|
|
|
|
static struct omap_hwmod omap44xx_iva_hwmod = {
|
|
.name = "iva",
|
|
.class = &omap44xx_iva_hwmod_class,
|
|
.clkdm_name = "ivahd_clkdm",
|
|
.rst_lines = omap44xx_iva_resets,
|
|
.rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
|
|
.main_clk = "dpll_iva_m5x2_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
|
|
.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'mpu' class
|
|
* mpu sub-system
|
|
*/
|
|
|
|
static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
|
|
.name = "mpu",
|
|
};
|
|
|
|
/* mpu */
|
|
static struct omap_hwmod omap44xx_mpu_hwmod = {
|
|
.name = "mpu",
|
|
.class = &omap44xx_mpu_hwmod_class,
|
|
.clkdm_name = "mpuss_clkdm",
|
|
.flags = HWMOD_INIT_NO_IDLE,
|
|
.main_clk = "dpll_mpu_m2_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'ocmc_ram' class
|
|
* top-level core on-chip ram
|
|
*/
|
|
|
|
static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
|
|
.name = "ocmc_ram",
|
|
};
|
|
|
|
/* ocmc_ram */
|
|
static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
|
|
.name = "ocmc_ram",
|
|
.class = &omap44xx_ocmc_ram_hwmod_class,
|
|
.clkdm_name = "l3_2_clkdm",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
|
|
},
|
|
},
|
|
};
|
|
|
|
|
|
/*
|
|
* 'prcm' class
|
|
* power and reset manager (part of the prcm infrastructure) + clock manager 2
|
|
* + clock manager 1 (in always on power domain) + local prm in mpu
|
|
*/
|
|
|
|
static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
|
|
.name = "prcm",
|
|
};
|
|
|
|
/* prcm_mpu */
|
|
static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
|
|
.name = "prcm_mpu",
|
|
.class = &omap44xx_prcm_hwmod_class,
|
|
.clkdm_name = "l4_wkup_clkdm",
|
|
.flags = HWMOD_NO_IDLEST,
|
|
.prcm = {
|
|
.omap4 = {
|
|
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* cm_core_aon */
|
|
static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
|
|
.name = "cm_core_aon",
|
|
.class = &omap44xx_prcm_hwmod_class,
|
|
.flags = HWMOD_NO_IDLEST,
|
|
.prcm = {
|
|
.omap4 = {
|
|
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* cm_core */
|
|
static struct omap_hwmod omap44xx_cm_core_hwmod = {
|
|
.name = "cm_core",
|
|
.class = &omap44xx_prcm_hwmod_class,
|
|
.flags = HWMOD_NO_IDLEST,
|
|
.prcm = {
|
|
.omap4 = {
|
|
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* prm */
|
|
static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
|
|
{ .name = "rst_global_warm_sw", .rst_shift = 0 },
|
|
{ .name = "rst_global_cold_sw", .rst_shift = 1 },
|
|
};
|
|
|
|
static struct omap_hwmod omap44xx_prm_hwmod = {
|
|
.name = "prm",
|
|
.class = &omap44xx_prcm_hwmod_class,
|
|
.rst_lines = omap44xx_prm_resets,
|
|
.rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
|
|
};
|
|
|
|
/*
|
|
* 'scrm' class
|
|
* system clock and reset manager
|
|
*/
|
|
|
|
static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
|
|
.name = "scrm",
|
|
};
|
|
|
|
/* scrm */
|
|
static struct omap_hwmod omap44xx_scrm_hwmod = {
|
|
.name = "scrm",
|
|
.class = &omap44xx_scrm_hwmod_class,
|
|
.clkdm_name = "l4_wkup_clkdm",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'sl2if' class
|
|
* shared level 2 memory interface
|
|
*/
|
|
|
|
static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
|
|
.name = "sl2if",
|
|
};
|
|
|
|
/* sl2if */
|
|
static struct omap_hwmod omap44xx_sl2if_hwmod = {
|
|
.name = "sl2if",
|
|
.class = &omap44xx_sl2if_hwmod_class,
|
|
.clkdm_name = "ivahd_clkdm",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'timer' class
|
|
* general purpose timer module with accurate 1ms tick
|
|
* This class contains several variants: ['timer_1ms', 'timer']
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
|
|
.name = "timer",
|
|
.sysc = &omap44xx_timer_1ms_sysc,
|
|
};
|
|
|
|
/* timer1 */
|
|
static struct omap_hwmod omap44xx_timer1_hwmod = {
|
|
.name = "timer1",
|
|
.class = &omap44xx_timer_1ms_hwmod_class,
|
|
.clkdm_name = "l4_wkup_clkdm",
|
|
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
|
|
.main_clk = "dmt1_clk_mux",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'usb_host_fs' class
|
|
* full-speed usb host controller
|
|
*/
|
|
|
|
/* The IP is not compliant to type1 / type2 scheme */
|
|
static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0210,
|
|
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
|
|
};
|
|
|
|
static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
|
|
.name = "usb_host_fs",
|
|
.sysc = &omap44xx_usb_host_fs_sysc,
|
|
};
|
|
|
|
/* usb_host_fs */
|
|
static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
|
|
.name = "usb_host_fs",
|
|
.class = &omap44xx_usb_host_fs_hwmod_class,
|
|
.clkdm_name = "l3_init_clkdm",
|
|
.main_clk = "usb_host_fs_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'usb_host_hs' class
|
|
* high-speed multi-port usb host controller
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
|
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
|
|
.name = "usb_host_hs",
|
|
.sysc = &omap44xx_usb_host_hs_sysc,
|
|
};
|
|
|
|
/* usb_host_hs */
|
|
static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
|
|
.name = "usb_host_hs",
|
|
.class = &omap44xx_usb_host_hs_hwmod_class,
|
|
.clkdm_name = "l3_init_clkdm",
|
|
.main_clk = "usb_host_hs_fck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
|
|
/*
|
|
* Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
|
|
* id: i660
|
|
*
|
|
* Description:
|
|
* In the following configuration :
|
|
* - USBHOST module is set to smart-idle mode
|
|
* - PRCM asserts idle_req to the USBHOST module ( This typically
|
|
* happens when the system is going to a low power mode : all ports
|
|
* have been suspended, the master part of the USBHOST module has
|
|
* entered the standby state, and SW has cut the functional clocks)
|
|
* - an USBHOST interrupt occurs before the module is able to answer
|
|
* idle_ack, typically a remote wakeup IRQ.
|
|
* Then the USB HOST module will enter a deadlock situation where it
|
|
* is no more accessible nor functional.
|
|
*
|
|
* Workaround:
|
|
* Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
|
|
*/
|
|
|
|
/*
|
|
* Errata: USB host EHCI may stall when entering smart-standby mode
|
|
* Id: i571
|
|
*
|
|
* Description:
|
|
* When the USBHOST module is set to smart-standby mode, and when it is
|
|
* ready to enter the standby state (i.e. all ports are suspended and
|
|
* all attached devices are in suspend mode), then it can wrongly assert
|
|
* the Mstandby signal too early while there are still some residual OCP
|
|
* transactions ongoing. If this condition occurs, the internal state
|
|
* machine may go to an undefined state and the USB link may be stuck
|
|
* upon the next resume.
|
|
*
|
|
* Workaround:
|
|
* Don't use smart standby; use only force standby,
|
|
* hence HWMOD_SWSUP_MSTANDBY
|
|
*/
|
|
|
|
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
|
};
|
|
|
|
/*
|
|
* 'usb_tll_hs' class
|
|
* usb_tll_hs module is the adapter on the usb_host_hs ports
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
|
|
SYSC_HAS_AUTOIDLE),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
|
|
.name = "usb_tll_hs",
|
|
.sysc = &omap44xx_usb_tll_hs_sysc,
|
|
};
|
|
|
|
static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
|
|
.name = "usb_tll_hs",
|
|
.class = &omap44xx_usb_tll_hs_hwmod_class,
|
|
.clkdm_name = "l3_init_clkdm",
|
|
.main_clk = "usb_tll_hs_ick",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
|
|
.context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* interfaces
|
|
*/
|
|
|
|
/* l3_main_1 -> dmm */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
|
|
.master = &omap44xx_l3_main_1_hwmod,
|
|
.slave = &omap44xx_dmm_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_SDMA,
|
|
};
|
|
|
|
/* mpu -> dmm */
|
|
static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
|
|
.master = &omap44xx_mpu_hwmod,
|
|
.slave = &omap44xx_dmm_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* iva -> l3_instr */
|
|
static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
|
|
.master = &omap44xx_iva_hwmod,
|
|
.slave = &omap44xx_l3_instr_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_3 -> l3_instr */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
|
|
.master = &omap44xx_l3_main_3_hwmod,
|
|
.slave = &omap44xx_l3_instr_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* ocp_wp_noc -> l3_instr */
|
|
static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
|
|
.master = &omap44xx_ocp_wp_noc_hwmod,
|
|
.slave = &omap44xx_l3_instr_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* dsp -> l3_main_1 */
|
|
static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
|
|
.master = &omap44xx_dsp_hwmod,
|
|
.slave = &omap44xx_l3_main_1_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* dss -> l3_main_1 */
|
|
static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
|
|
.master = &omap44xx_dss_hwmod,
|
|
.slave = &omap44xx_l3_main_1_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_2 -> l3_main_1 */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_l3_main_1_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> l3_main_1 */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
.slave = &omap44xx_l3_main_1_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* mpu -> l3_main_1 */
|
|
static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
|
|
.master = &omap44xx_mpu_hwmod,
|
|
.slave = &omap44xx_l3_main_1_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* debugss -> l3_main_2 */
|
|
static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
|
|
.master = &omap44xx_debugss_hwmod,
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
.clk = "dbgclk_mux_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* ipu -> l3_main_2 */
|
|
static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
|
|
.master = &omap44xx_ipu_hwmod,
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* iss -> l3_main_2 */
|
|
static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
|
|
.master = &omap44xx_iss_hwmod,
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* iva -> l3_main_2 */
|
|
static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
|
|
.master = &omap44xx_iva_hwmod,
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> l3_main_2 */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
|
|
.master = &omap44xx_l3_main_1_hwmod,
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l4_cfg -> l3_main_2 */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* usb_host_fs -> l3_main_2 */
|
|
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
|
|
.master = &omap44xx_usb_host_fs_hwmod,
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* usb_host_hs -> l3_main_2 */
|
|
static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
|
|
.master = &omap44xx_usb_host_hs_hwmod,
|
|
.slave = &omap44xx_l3_main_2_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> l3_main_3 */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
|
|
.master = &omap44xx_l3_main_1_hwmod,
|
|
.slave = &omap44xx_l3_main_3_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l3_main_2 -> l3_main_3 */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_l3_main_3_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> l3_main_3 */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
.slave = &omap44xx_l3_main_3_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* dsp -> l4_abe */
|
|
static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
|
|
.master = &omap44xx_dsp_hwmod,
|
|
.slave = &omap44xx_l4_abe_hwmod,
|
|
.clk = "ocp_abe_iclk",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> l4_abe */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
|
|
.master = &omap44xx_l3_main_1_hwmod,
|
|
.slave = &omap44xx_l4_abe_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* mpu -> l4_abe */
|
|
static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
|
|
.master = &omap44xx_mpu_hwmod,
|
|
.slave = &omap44xx_l4_abe_hwmod,
|
|
.clk = "ocp_abe_iclk",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> l4_cfg */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
|
|
.master = &omap44xx_l3_main_1_hwmod,
|
|
.slave = &omap44xx_l4_cfg_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_2 -> l4_per */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_l4_per_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> l4_wkup */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
.slave = &omap44xx_l4_wkup_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* mpu -> mpu_private */
|
|
static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
|
|
.master = &omap44xx_mpu_hwmod,
|
|
.slave = &omap44xx_mpu_private_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> ocp_wp_noc */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
.slave = &omap44xx_ocp_wp_noc_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> counter_32k */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
.slave = &omap44xx_counter_32k_hwmod,
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> ctrl_module_core */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
.slave = &omap44xx_ctrl_module_core_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> ctrl_module_pad_core */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
.slave = &omap44xx_ctrl_module_pad_core_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> ctrl_module_wkup */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
.slave = &omap44xx_ctrl_module_wkup_hwmod,
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> ctrl_module_pad_wkup */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
.slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_instr -> debugss */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
|
|
.master = &omap44xx_l3_instr_hwmod,
|
|
.slave = &omap44xx_debugss_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* dsp -> iva */
|
|
static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
|
|
.master = &omap44xx_dsp_hwmod,
|
|
.slave = &omap44xx_iva_hwmod,
|
|
.clk = "dpll_iva_m5x2_ck",
|
|
.user = OCP_USER_DSP,
|
|
};
|
|
|
|
/* dsp -> sl2if */
|
|
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
|
|
.master = &omap44xx_dsp_hwmod,
|
|
.slave = &omap44xx_sl2if_hwmod,
|
|
.clk = "dpll_iva_m5x2_ck",
|
|
.user = OCP_USER_DSP,
|
|
};
|
|
|
|
/* l4_cfg -> dsp */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
.slave = &omap44xx_dsp_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_2 -> dss */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_dss_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per -> dss */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
.slave = &omap44xx_dss_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l3_main_2 -> dss_dispc */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_dss_dispc_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per -> dss_dispc */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
.slave = &omap44xx_dss_dispc_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l3_main_2 -> dss_dsi1 */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_dss_dsi1_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per -> dss_dsi1 */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
.slave = &omap44xx_dss_dsi1_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l3_main_2 -> dss_dsi2 */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_dss_dsi2_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per -> dss_dsi2 */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
.slave = &omap44xx_dss_dsi2_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l3_main_2 -> dss_hdmi */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_dss_hdmi_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per -> dss_hdmi */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
.slave = &omap44xx_dss_hdmi_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l3_main_2 -> dss_rfbi */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_dss_rfbi_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per -> dss_rfbi */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
.slave = &omap44xx_dss_rfbi_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l3_main_2 -> dss_venc */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_dss_venc_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per -> dss_venc */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
|
|
.master = &omap44xx_l4_per_hwmod,
|
|
.slave = &omap44xx_dss_venc_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l3_main_2 -> gpmc */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_gpmc_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_2 -> ipu */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_ipu_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_2 -> iss */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_iss_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* iva -> sl2if */
|
|
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
|
|
.master = &omap44xx_iva_hwmod,
|
|
.slave = &omap44xx_sl2if_hwmod,
|
|
.clk = "dpll_iva_m5x2_ck",
|
|
.user = OCP_USER_IVA,
|
|
};
|
|
|
|
/* l3_main_2 -> iva */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_iva_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l3_main_2 -> ocmc_ram */
|
|
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_ocmc_ram_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* mpu_private -> prcm_mpu */
|
|
static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
|
|
.master = &omap44xx_mpu_private_hwmod,
|
|
.slave = &omap44xx_prcm_mpu_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> cm_core_aon */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
.slave = &omap44xx_cm_core_aon_hwmod,
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> cm_core */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
.slave = &omap44xx_cm_core_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> prm */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
.slave = &omap44xx_prm_hwmod,
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> scrm */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
.slave = &omap44xx_scrm_hwmod,
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_2 -> sl2if */
|
|
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
|
|
.master = &omap44xx_l3_main_2_hwmod,
|
|
.slave = &omap44xx_sl2if_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> timer1 */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
|
|
.master = &omap44xx_l4_wkup_hwmod,
|
|
.slave = &omap44xx_timer1_hwmod,
|
|
.clk = "l4_wkup_clk_mux_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> usb_host_fs */
|
|
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
.slave = &omap44xx_usb_host_fs_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> usb_host_hs */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
.slave = &omap44xx_usb_host_hs_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> usb_tll_hs */
|
|
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
|
|
.master = &omap44xx_l4_cfg_hwmod,
|
|
.slave = &omap44xx_usb_tll_hs_hwmod,
|
|
.clk = "l4_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* mpu -> emif1 */
|
|
static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
|
|
.master = &omap44xx_mpu_hwmod,
|
|
.slave = &omap44xx_emif1_hwmod,
|
|
.clk = "l3_div_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* mpu -> emif2 */
|
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static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
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.master = &omap44xx_mpu_hwmod,
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.slave = &omap44xx_emif2_hwmod,
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.clk = "l3_div_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
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&omap44xx_l3_main_1__dmm,
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&omap44xx_mpu__dmm,
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&omap44xx_iva__l3_instr,
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&omap44xx_l3_main_3__l3_instr,
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&omap44xx_ocp_wp_noc__l3_instr,
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&omap44xx_dsp__l3_main_1,
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&omap44xx_dss__l3_main_1,
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&omap44xx_l3_main_2__l3_main_1,
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&omap44xx_l4_cfg__l3_main_1,
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&omap44xx_mpu__l3_main_1,
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&omap44xx_debugss__l3_main_2,
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&omap44xx_ipu__l3_main_2,
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&omap44xx_iss__l3_main_2,
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&omap44xx_iva__l3_main_2,
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&omap44xx_l3_main_1__l3_main_2,
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&omap44xx_l4_cfg__l3_main_2,
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/* &omap44xx_usb_host_fs__l3_main_2, */
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&omap44xx_usb_host_hs__l3_main_2,
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&omap44xx_l3_main_1__l3_main_3,
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&omap44xx_l3_main_2__l3_main_3,
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&omap44xx_l4_cfg__l3_main_3,
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&omap44xx_dsp__l4_abe,
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&omap44xx_l3_main_1__l4_abe,
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&omap44xx_mpu__l4_abe,
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&omap44xx_l3_main_1__l4_cfg,
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&omap44xx_l3_main_2__l4_per,
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&omap44xx_l4_cfg__l4_wkup,
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&omap44xx_mpu__mpu_private,
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&omap44xx_l4_cfg__ocp_wp_noc,
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&omap44xx_l4_wkup__counter_32k,
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&omap44xx_l4_cfg__ctrl_module_core,
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&omap44xx_l4_cfg__ctrl_module_pad_core,
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&omap44xx_l4_wkup__ctrl_module_wkup,
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&omap44xx_l4_wkup__ctrl_module_pad_wkup,
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&omap44xx_l3_instr__debugss,
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&omap44xx_dsp__iva,
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/* &omap44xx_dsp__sl2if, */
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&omap44xx_l4_cfg__dsp,
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&omap44xx_l3_main_2__dss,
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&omap44xx_l4_per__dss,
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&omap44xx_l3_main_2__dss_dispc,
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&omap44xx_l4_per__dss_dispc,
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&omap44xx_l3_main_2__dss_dsi1,
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&omap44xx_l4_per__dss_dsi1,
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&omap44xx_l3_main_2__dss_dsi2,
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&omap44xx_l4_per__dss_dsi2,
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&omap44xx_l3_main_2__dss_hdmi,
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&omap44xx_l4_per__dss_hdmi,
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&omap44xx_l3_main_2__dss_rfbi,
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&omap44xx_l4_per__dss_rfbi,
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&omap44xx_l3_main_2__dss_venc,
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&omap44xx_l4_per__dss_venc,
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&omap44xx_l3_main_2__gpmc,
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&omap44xx_l3_main_2__ipu,
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&omap44xx_l3_main_2__iss,
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/* &omap44xx_iva__sl2if, */
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&omap44xx_l3_main_2__iva,
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&omap44xx_l3_main_2__ocmc_ram,
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&omap44xx_mpu_private__prcm_mpu,
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&omap44xx_l4_wkup__cm_core_aon,
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&omap44xx_l4_cfg__cm_core,
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&omap44xx_l4_wkup__prm,
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&omap44xx_l4_wkup__scrm,
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/* &omap44xx_l3_main_2__sl2if, */
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&omap44xx_l4_wkup__timer1,
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/* &omap44xx_l4_cfg__usb_host_fs, */
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&omap44xx_l4_cfg__usb_host_hs,
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&omap44xx_l4_cfg__usb_tll_hs,
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&omap44xx_mpu__emif1,
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&omap44xx_mpu__emif2,
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NULL,
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};
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int __init omap44xx_hwmod_init(void)
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{
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omap_hwmod_init();
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return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
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}
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