Mike Marciniszyn 06e81e3e92 IB/hfi1: Remove caches of chip CSRs ... Remove the sizeable cache of the chip sizing CSRs and replace with CSR reads as needed. Reviewed-by: Michael J. Ruhl <michael.j.ruhl@intel.com> Signed-off-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>		2018-06-22 09:12:17 -06:00
..
core	IB/core: Free GID table entry during GID deletion	2018-06-22 09:02:59 -06:00
hw	IB/hfi1: Remove caches of chip CSRs	2018-06-22 09:12:17 -06:00
sw	IB/core: add max_send_sge and max_recv_sge attributes	2018-06-18 13:17:28 -06:00
ulp	IB/core: add max_send_sge and max_recv_sge attributes	2018-06-18 13:17:28 -06:00
Kconfig	RDMA/ucm: Mark UCM interface as BROKEN	2018-05-24 09:39:25 -06:00
Makefile	IB/rdmavt: Create module framework and handle driver registration	2016-03-10 20:37:04 -05:00