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Add the chip-level device tree, including binding headers, for the NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices are initially available, enough to boot to UART console. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
36 lines
1.2 KiB
C
36 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
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#ifndef __ABI_MACH_T194_POWERGATE_T194_H_
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#define __ABI_MACH_T194_POWERGATE_T194_H_
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#define TEGRA194_POWER_DOMAIN_AUD 1
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#define TEGRA194_POWER_DOMAIN_DISP 2
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#define TEGRA194_POWER_DOMAIN_DISPB 3
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#define TEGRA194_POWER_DOMAIN_DISPC 4
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#define TEGRA194_POWER_DOMAIN_ISPA 5
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#define TEGRA194_POWER_DOMAIN_NVDECA 6
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#define TEGRA194_POWER_DOMAIN_NVJPG 7
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#define TEGRA194_POWER_DOMAIN_NVENCA 8
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#define TEGRA194_POWER_DOMAIN_NVENCB 9
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#define TEGRA194_POWER_DOMAIN_NVDECB 10
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#define TEGRA194_POWER_DOMAIN_SAX 11
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#define TEGRA194_POWER_DOMAIN_VE 12
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#define TEGRA194_POWER_DOMAIN_VIC 13
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#define TEGRA194_POWER_DOMAIN_XUSBA 14
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#define TEGRA194_POWER_DOMAIN_XUSBB 15
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#define TEGRA194_POWER_DOMAIN_XUSBC 16
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#define TEGRA194_POWER_DOMAIN_PCIEX8A 17
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#define TEGRA194_POWER_DOMAIN_PCIEX4A 18
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#define TEGRA194_POWER_DOMAIN_PCIEX1A 19
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#define TEGRA194_POWER_DOMAIN_PCIEX8B 21
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#define TEGRA194_POWER_DOMAIN_PVAA 22
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#define TEGRA194_POWER_DOMAIN_PVAB 23
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#define TEGRA194_POWER_DOMAIN_DLAA 24
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#define TEGRA194_POWER_DOMAIN_DLAB 25
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#define TEGRA194_POWER_DOMAIN_CV 26
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#define TEGRA194_POWER_DOMAIN_GPU 27
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#define TEGRA194_POWER_DOMAIN_MAX 27
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#endif
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