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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b0d8003ef4
Mostly complete rewrite of the FRV atomic implementation, instead of
using assembly files, use inline assembler.
The out-of-line CONFIG option makes a bit of a mess of things, but a
little CPP trickery gets that done too.
FRV already had the atomic logic ops but under a non standard name,
the reimplementation provides the generic names and provides the
intermediate form required for the bitops implementation.
The slightly inconsistent __atomic32_fetch_##op naming is because
__atomic_fetch_##op conlicts with GCC builtin functions.
The 64bit atomic ops use the inline assembly %Ln construct to access
the low word register (r+1), afaik this construct was not previously
used in the kernel and is completely undocumented, but I found it in
the FRV GCC code and it seems to work.
FRV had a non-standard definition of atomic_{clear,set}_mask() which
would work types other than atomic_t, the one user relying on that
(arch/frv/kernel/dma.c) got converted to use the new intermediate
form.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
63 lines
1.7 KiB
ArmAsm
63 lines
1.7 KiB
ArmAsm
/* atomic-ops.S: kernel atomic operations
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*
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* For an explanation of how atomic ops work in this arch, see:
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* Documentation/frv/atomic-ops.txt
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/spr-regs.h>
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.text
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.balign 4
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###############################################################################
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#
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# uint32_t __xchg_32(uint32_t i, uint32_t *v)
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#
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###############################################################################
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.globl __xchg_32
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.type __xchg_32,@function
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__xchg_32:
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or.p gr8,gr8,gr10
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0:
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orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
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ckeq icc3,cc7
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ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
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orcr cc7,cc7,cc3 /* set CC3 to true */
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cst.p gr10,@(gr9,gr0) ,cc3,#1
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corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
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beq icc3,#0,0b
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bralr
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.size __xchg_32, .-__xchg_32
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###############################################################################
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#
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# uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new)
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#
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###############################################################################
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.globl __cmpxchg_32
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.type __cmpxchg_32,@function
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__cmpxchg_32:
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or.p gr8,gr8,gr11
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0:
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orcc gr0,gr0,gr0,icc3
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ckeq icc3,cc7
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ld.p @(gr11,gr0),gr8
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orcr cc7,cc7,cc3
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subcc gr8,gr9,gr7,icc0
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bnelr icc0,#0
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cst.p gr10,@(gr11,gr0) ,cc3,#1
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corcc gr29,gr29,gr0 ,cc3,#1
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beq icc3,#0,0b
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bralr
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.size __cmpxchg_32, .-__cmpxchg_32
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