Sung Lee 06535a48e2 drm/amd/display: Cap certain DML values for Low Pix Clk on DCN2.1 ... [WHY] In certain conditions with low pixel clock, some values in DML may go past the max due to margining for latency hiding. This causes assertions to get hit. [HOW] If the pixel clock is low and some values are high, cap it to the max. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-04-22 18:11:48 -04:00
..
amdgpu_dm	drm/amd/display: Use the correct input TF for video formats	2020-04-22 18:11:47 -04:00
dc	drm/amd/display: Cap certain DML values for Low Pix Clk on DCN2.1	2020-04-22 18:11:48 -04:00
dmub	drm/amd/display: Various fixes for PSR on DMCUB	2020-04-22 18:11:48 -04:00
include	drm/amd/display: query hdcp capability during link detect	2020-04-09 10:43:17 -04:00
modules	drm/amd/display: Change infopacket type programming	2020-04-22 18:11:47 -04:00
Kconfig	amdgpu: Enable initial DCN support on POWER	2019-12-18 16:09:05 -05:00
Makefile	drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards	2019-11-13 15:29:42 -05:00
TODO