Christophe Leroy 060ef9d89d powerpc32: PAGE_EXEC required for inittext ... PAGE_EXEC is required for inittext, otherwise CONFIG_DEBUG_PAGEALLOC ends up with an Oops [ 0.000000] Inode-cache hash table entries: 8192 (order: 1, 32768 bytes) [ 0.000000] Sorting __ex_table... [ 0.000000] bootmem::free_all_bootmem_core nid=0 start=0 end=2000 [ 0.000000] Unable to handle kernel paging request for instruction fetch [ 0.000000] Faulting instruction address: 0xc045b970 [ 0.000000] Oops: Kernel access of bad area, sig: 11 [#1] [ 0.000000] PREEMPT DEBUG_PAGEALLOC CMPC885 [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 3.18.25-local-dirty #1673 [ 0.000000] task: c04d83d0 ti: c04f8000 task.ti: c04f8000 [ 0.000000] NIP: c045b970 LR: c045b970 CTR: 0000000a [ 0.000000] REGS: c04f9ea0 TRAP: 0400 Not tainted (3.18.25-local-dirty) [ 0.000000] MSR: 08001032 <ME,IR,DR,RI> CR: 39955d35 XER: a000ff40 [ 0.000000] GPR00: c045b970 c04f9f50 c04d83d0 00000000 ffffffff c04dcdf4 00000048 c04f6b10 GPR08: c04f6ab0 00000001 c0563488 c04f6ab0 c04f8000 00000000 00000000 b6db6db7 GPR16: 00003474 00000180 00002000 c7fec000 00000000 000003ff 00000176 c0415014 GPR24: c0471018 c0414ee8 c05304e8 c03aeaac c0510000 c0471018 c0471010 00000000 [ 0.000000] NIP [c045b970] free_all_bootmem+0x164/0x228 [ 0.000000] LR [c045b970] free_all_bootmem+0x164/0x228 [ 0.000000] Call Trace: [ 0.000000] [c04f9f50] [c045b970] free_all_bootmem+0x164/0x228 (unreliable) [ 0.000000] [c04f9fa0] [c0454044] mem_init+0x3c/0xd0 [ 0.000000] [c04f9fb0] [c045080c] start_kernel+0x1f4/0x390 [ 0.000000] [c04f9ff0] [c0002214] start_here+0x38/0x98 [ 0.000000] Instruction dump: [ 0.000000] 2f150000 7f968840 72a90001 3ad60001 56b5f87e 419a0028 419e0024 41a20018 [ 0.000000] 807cc20c 38800000 7c638214 4bffd2f5 <3a940001> 3a100024 4bffffc8 7e368b78 [ 0.000000] ---[ end trace dc8fa200cb88537f ]--- Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>		2016-03-11 20:04:32 -06:00
..
8xx_mmu.c	powerpc/8xx: rewrite flush_instruction_cache() in C	2016-03-11 17:20:11 -06:00
40x_mmu.c	powerpc/mm: Don't use pmd_val, pud_val and pgd_val as lvalue	2015-12-14 15:19:07 +11:00
44x_mmu.c
copro_fault.c	cxl: Move include file cxl.h -> cxl-base.h	2015-06-03 13:27:19 +10:00
dma-noncoherent.c	powerpc: Simplify test in __dma_sync()	2016-03-11 17:20:12 -06:00
fault.c	powerpc: Add plain English description for alignment exception oopses	2015-07-06 20:24:35 +10:00
fsl_booke_mmu.c	powerpc32: refactor x_mapped_by_bats() and x_mapped_by_tlbcam() together	2016-03-11 17:18:02 -06:00
hash64_4k.c	powerpc/mm: add _PAGE_HASHPTE similar to 4K hash	2016-03-03 21:18:29 +11:00
hash64_64k.c	powerp/mm: Update code comments	2016-03-03 21:18:29 +11:00
hash_low_32.S
hash_native_64.c	powerpc/mm: Move THP headers around	2015-12-14 15:19:14 +11:00
hash_utils_64.c	powerpc/mm: Split hash page table sizing heuristic into a helper	2016-03-02 09:06:16 +11:00
highmem.c	sched/preempt, mm/kmap: Explicitly disable/enable preemption in kmap_atomic_*	2015-05-19 08:39:14 +02:00
hugepage-hash64.c	powerpc/mm/hash: Clear the invalid slot information correctly	2016-02-22 19:27:39 +11:00
hugetlbpage-book3e.c	powerpc/e6500: add locking to hugetlb	2015-12-22 18:23:22 -06:00
hugetlbpage-hash64.c	powerpc/mm/book3s-64: Move HPTE-related bits in PTE to upper end	2016-02-29 20:34:39 +11:00
hugetlbpage.c	powerpc/mm/book3s-64: Use physical addresses in upper page table tree levels	2016-02-29 20:34:34 +11:00
icswx_pid.c
icswx.c
icswx.h
init_32.c	powerpc32: Remove useless/wrong MMU:setio progress message	2016-03-11 17:18:02 -06:00
init_64.c	powerpc/mm: Switch book3s 64 with 64K page size to 4 level page table	2016-03-03 21:18:28 +11:00
Makefile	powerpc/8xx: Map linear kernel RAM with 8M pages	2016-03-11 17:18:01 -06:00
mem.c	powerpc/mm: Clean up memory hotplug failure paths	2016-03-01 22:04:18 +11:00
mmap.c	mm: expose arch_mmap_rnd when available	2015-04-14 16:49:05 -07:00
mmu_context_hash32.c	powerpc: Remove power3 from comments	2014-07-28 14:10:26 +10:00
mmu_context_hash64.c	powerpc/mmu: Add userspace-to-physical addresses translation cache	2015-06-11 15:16:54 +10:00
mmu_context_iommu.c	powerpc/mmu: Add userspace-to-physical addresses translation cache	2015-06-11 15:16:54 +10:00
mmu_context_nohash.c	powerpc/8xx: reduce pressure on TLB due to context switches	2015-01-29 21:51:06 -06:00
mmu_decl.h	powerpc32: remove ioremap_base	2016-03-11 17:18:02 -06:00
numa.c	powerpc updates for 4.4	2015-11-05 23:38:43 -08:00
pgtable_32.c	powerpc32: PAGE_EXEC required for inittext	2016-03-11 20:04:32 -06:00
pgtable_64.c	mm: Some arch may want to use HPAGE_PMD related values as variables	2016-03-03 21:18:29 +11:00
pgtable.c	powerpc/mm: Add a _PAGE_PTE bit	2015-12-14 15:19:14 +11:00
ppc_mmu_32.c	powerpc32: refactor x_mapped_by_bats() and x_mapped_by_tlbcam() together	2016-03-11 17:18:02 -06:00
slb_low.S
slb.c	powerpc: Add function to copy mm_context_t to the paca	2015-12-19 22:13:12 +11:00
slice.c	powerpc: Add function to copy mm_context_t to the paca	2015-12-19 22:13:12 +11:00
subpage-prot.c	thp: rename split_huge_page_pmd() to split_huge_pmd()	2016-01-15 17:56:32 -08:00
tlb_hash32.c
tlb_hash64.c	powerpc/mm: Differentiate between hugetlb and THP during page walk	2015-10-12 15:30:09 +11:00
tlb_low_64e.S	powerpc: Fix misspellings in comments.	2016-03-01 19:27:20 +11:00
tlb_nohash_low.S	powerpc: Fix misspellings in comments.	2016-03-01 19:27:20 +11:00
tlb_nohash.c	powerpc/mm: any thread in one core can be the first to setup TLB1	2016-03-04 23:44:02 -06:00
vphn.c	powerpc/vphn: parsing code rewrite	2015-03-18 10:48:59 +11:00
vphn.h	powerpc/vphn: parsing code rewrite	2015-03-18 10:48:59 +11:00