mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
6c9da387c8
The CRG(Clock and Reset Generator) block provides clock and reset signals for other modules in hi3519 soc. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
||
|---|---|---|
| .. | ||
| clk-hi3519.c | ||
| clk-hi3620.c | ||
| clk-hi6220-stub.c | ||
| clk-hi6220.c | ||
| clk-hip04.c | ||
| clk-hix5hd2.c | ||
| clk.c | ||
| clk.h | ||
| clkdivider-hi6220.c | ||
| clkgate-separated.c | ||
| Kconfig | ||
| Makefile | ||
| reset.c | ||
| reset.h | ||