mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
05f814402d
Fdiv fixed dividers clocks of the fixed_pll can actually gate independently. We never had an issue so far because these clocks were provided 'enabled' by the bootloader. Add these gates to enable/disable the clocks when required. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
||
---|---|---|
.. | ||
axg.c | ||
axg.h | ||
clk-audio-divider.c | ||
clk-mpll.c | ||
clk-pll.c | ||
clk-regmap.c | ||
clk-regmap.h | ||
clkc.h | ||
gxbb-aoclk-32k.c | ||
gxbb-aoclk.c | ||
gxbb-aoclk.h | ||
gxbb.c | ||
gxbb.h | ||
Kconfig | ||
Makefile | ||
meson8b.c | ||
meson8b.h |