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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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05ee321511
Send the VBIOS bootup VDDC as a SOC floor voltage to SMU before populating the PPTABLE. After DPM is enabled, This floor voltage will be removed. This will prevent SMC from going to Vmin upon receiving PPTable causing a violation. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
156 lines
5.1 KiB
C
156 lines
5.1 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef PP_ATOMFWCTRL_H
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#define PP_ATOMFWCTRL_H
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#include "hwmgr.h"
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#define GetIndexIntoMasterCmdTable(FieldName) \
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(((char*)(&((struct atom_master_list_of_command_functions_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
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#define GetIndexIntoMasterDataTable(FieldName) \
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(((char*)(&((struct atom_master_list_of_data_tables_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
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#define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES 32
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struct pp_atomfwctrl_voltage_table_entry {
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uint16_t value;
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uint32_t smio_low;
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};
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struct pp_atomfwctrl_voltage_table {
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uint32_t count;
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uint32_t mask_low;
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uint32_t phase_delay;
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uint8_t psi0_enable;
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uint8_t psi1_enable;
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uint8_t max_vid_step;
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uint8_t telemetry_offset;
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uint8_t telemetry_slope;
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struct pp_atomfwctrl_voltage_table_entry entries[PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES];
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};
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struct pp_atomfwctrl_gpio_pin_assignment {
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uint16_t us_gpio_pin_aindex;
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uint8_t uc_gpio_pin_bit_shift;
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};
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struct pp_atomfwctrl_clock_dividers_soc15 {
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uint32_t ulClock; /* the actual clock */
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uint32_t ulDid; /* DFS divider */
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uint32_t ulPll_fb_mult; /* Feedback Multiplier: bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
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uint32_t ulPll_ss_fbsmult; /* Spread FB Multiplier: bit 8:0 int, bit 31:16 frac */
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uint16_t usPll_ss_slew_frac;
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uint8_t ucPll_ss_enable;
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uint8_t ucReserve;
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uint32_t ulReserve[2];
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};
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struct pp_atomfwctrl_avfs_parameters {
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uint32_t ulMaxVddc;
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uint32_t ulMinVddc;
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uint32_t ulMeanNsigmaAcontant0;
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uint32_t ulMeanNsigmaAcontant1;
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uint32_t ulMeanNsigmaAcontant2;
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uint16_t usMeanNsigmaDcTolSigma;
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uint16_t usMeanNsigmaPlatformMean;
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uint16_t usMeanNsigmaPlatformSigma;
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uint32_t ulGbVdroopTableCksoffA0;
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uint32_t ulGbVdroopTableCksoffA1;
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uint32_t ulGbVdroopTableCksoffA2;
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uint32_t ulGbVdroopTableCksonA0;
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uint32_t ulGbVdroopTableCksonA1;
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uint32_t ulGbVdroopTableCksonA2;
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uint32_t ulGbFuseTableCksoffM1;
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uint32_t ulGbFuseTableCksoffM2;
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uint32_t ulGbFuseTableCksoffB;
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uint32_t ulGbFuseTableCksonM1;
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uint32_t ulGbFuseTableCksonM2;
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uint32_t ulGbFuseTableCksonB;
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uint8_t ucEnableGbVdroopTableCkson;
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uint8_t ucEnableGbFuseTableCkson;
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uint16_t usPsmAgeComfactor;
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uint32_t ulDispclk2GfxclkM1;
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uint32_t ulDispclk2GfxclkM2;
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uint32_t ulDispclk2GfxclkB;
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uint32_t ulDcefclk2GfxclkM1;
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uint32_t ulDcefclk2GfxclkM2;
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uint32_t ulDcefclk2GfxclkB;
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uint32_t ulPixelclk2GfxclkM1;
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uint32_t ulPixelclk2GfxclkM2;
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uint32_t ulPixelclk2GfxclkB;
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uint32_t ulPhyclk2GfxclkM1;
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uint32_t ulPhyclk2GfxclkM2;
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uint32_t ulPhyclk2GfxclkB;
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};
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struct pp_atomfwctrl_gpio_parameters {
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uint8_t ucAcDcGpio;
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uint8_t ucAcDcPolarity;
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uint8_t ucVR0HotGpio;
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uint8_t ucVR0HotPolarity;
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uint8_t ucVR1HotGpio;
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uint8_t ucVR1HotPolarity;
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uint8_t ucFwCtfGpio;
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uint8_t ucFwCtfPolarity;
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};
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struct pp_atomfwctrl_bios_boot_up_values {
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uint32_t ulRevision;
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uint32_t ulGfxClk;
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uint32_t ulUClk;
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uint32_t ulSocClk;
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uint16_t usVddc;
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uint16_t usVddci;
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uint16_t usMvddc;
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uint16_t usVddGfx;
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};
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int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
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uint32_t clock_type, uint32_t clock_value,
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struct pp_atomfwctrl_clock_dividers_soc15 *dividers);
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int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr);
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bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id,
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struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment);
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int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
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uint8_t voltage_mode, struct pp_atomfwctrl_voltage_table *voltage_table);
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bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
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uint8_t voltage_type, uint8_t voltage_mode);
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int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
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struct pp_atomfwctrl_avfs_parameters *param);
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int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
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struct pp_atomfwctrl_gpio_parameters *param);
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int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
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struct pp_atomfwctrl_bios_boot_up_values *boot_values);
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#endif
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