mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 10:06:43 +07:00
0f45d7f36b
There is no FSR/FAR register on no-CP15 or MPU cores. This patch adds a dummy abort handler which returns zero for the base restored Data Abort model !CPU_CP15_MMU cores. The abort-lv4t.S is still used with the fix-up for the base updated Data Abort model cores. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
226 lines
6.4 KiB
ArmAsm
226 lines
6.4 KiB
ArmAsm
#include <linux/linkage.h>
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#include <asm/assembler.h>
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/*
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* Function: v4t_late_abort
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*
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* Params : r2 = address of aborted instruction
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* : r3 = saved SPSR
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*
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* Returns : r0 = address of abort
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* : r1 = FSR, bit 11 = write
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* : r2-r8 = corrupted
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* : r9 = preserved
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* : sp = pointer to registers
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*
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* Purpose : obtain information about current aborted instruction.
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* Note: we read user space. This means we might cause a data
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* abort here if the I-TLB and D-TLB aren't seeing the same
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* picture. Unfortunately, this does happen. We live with it.
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*/
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ENTRY(v4t_late_abort)
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tst r3, #PSR_T_BIT @ check for thumb mode
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#ifdef CONFIG_CPU_CP15_MMU
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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#else
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mov r0, #0 @ clear r0, r1 (no FSR/FAR)
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mov r1, #0
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#endif
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bne .data_thumb_abort
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ldr r8, [r2] @ read arm instruction
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tst r8, #1 << 20 @ L = 1 -> write?
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orreq r1, r1, #1 << 11 @ yes.
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and r7, r8, #15 << 24
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add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
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nop
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/* 0 */ b .data_arm_lateldrhpost @ ldrh rd, [rn], #m/rm
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/* 1 */ b .data_arm_lateldrhpre @ ldrh rd, [rn, #m/rm]
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/* 2 */ b .data_unknown
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/* 3 */ b .data_unknown
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/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
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/* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
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/* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
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/* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
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/* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist>
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/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
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/* a */ b .data_unknown
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/* b */ b .data_unknown
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/* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
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/* d */ mov pc, lr @ ldc rd, [rn, #m]
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/* e */ b .data_unknown
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/* f */
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.data_unknown: @ Part of jumptable
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mov r0, r2
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mov r1, r8
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mov r2, sp
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bl baddataabort
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b ret_from_exception
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.data_arm_ldmstm:
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tst r8, #1 << 21 @ check writeback bit
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moveq pc, lr @ no writeback -> no fixup
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mov r7, #0x11
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orr r7, r7, #0x1100
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and r6, r8, r7
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and r2, r8, r7, lsl #1
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add r6, r6, r2, lsr #1
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and r2, r8, r7, lsl #2
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add r6, r6, r2, lsr #2
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and r2, r8, r7, lsl #3
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add r6, r6, r2, lsr #3
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add r6, r6, r6, lsr #8
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add r6, r6, r6, lsr #4
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and r6, r6, #15 @ r6 = no. of registers to transfer.
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6, lsl #2 @ Undo increment
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addeq r7, r7, r6, lsl #2 @ Undo decrement
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str r7, [sp, r5, lsr #14] @ Put register 'Rn'
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mov pc, lr
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.data_arm_lateldrhpre:
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tst r8, #1 << 21 @ Check writeback bit
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moveq pc, lr @ No writeback -> no fixup
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.data_arm_lateldrhpost:
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and r5, r8, #0x00f @ get Rm / low nibble of immediate value
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tst r8, #1 << 22 @ if (immediate offset)
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andne r6, r8, #0xf00 @ { immediate high nibble
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orrne r6, r5, r6, lsr #4 @ combine nibbles } else
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ldreq r6, [sp, r5, lsl #2] @ { load Rm value }
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.data_arm_apply_r6_and_rn:
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r6 @ Undo incrmenet
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addeq r7, r7, r6 @ Undo decrement
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str r7, [sp, r5, lsr #14] @ Put register 'Rn'
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mov pc, lr
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.data_arm_lateldrpreconst:
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tst r8, #1 << 21 @ check writeback bit
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moveq pc, lr @ no writeback -> no fixup
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.data_arm_lateldrpostconst:
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movs r2, r8, lsl #20 @ Get offset
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moveq pc, lr @ zero -> no fixup
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and r5, r8, #15 << 16 @ Extract 'n' from instruction
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ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
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tst r8, #1 << 23 @ Check U bit
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subne r7, r7, r2, lsr #20 @ Undo increment
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addeq r7, r7, r2, lsr #20 @ Undo decrement
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str r7, [sp, r5, lsr #14] @ Put register 'Rn'
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mov pc, lr
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.data_arm_lateldrprereg:
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tst r8, #1 << 21 @ check writeback bit
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moveq pc, lr @ no writeback -> no fixup
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.data_arm_lateldrpostreg:
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and r7, r8, #15 @ Extract 'm' from instruction
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ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
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mov r5, r8, lsr #7 @ get shift count
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ands r5, r5, #31
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and r7, r8, #0x70 @ get shift type
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orreq r7, r7, #8 @ shift count = 0
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add pc, pc, r7
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nop
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mov r6, r6, lsl r5 @ 0: LSL #!0
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b .data_arm_apply_r6_and_rn
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b .data_arm_apply_r6_and_rn @ 1: LSL #0
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nop
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b .data_unknown @ 2: MUL?
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nop
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b .data_unknown @ 3: MUL?
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nop
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mov r6, r6, lsr r5 @ 4: LSR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, lsr #32 @ 5: LSR #32
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b .data_arm_apply_r6_and_rn
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b .data_unknown @ 6: MUL?
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nop
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b .data_unknown @ 7: MUL?
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nop
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mov r6, r6, asr r5 @ 8: ASR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, asr #32 @ 9: ASR #32
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b .data_arm_apply_r6_and_rn
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b .data_unknown @ A: MUL?
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nop
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b .data_unknown @ B: MUL?
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nop
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mov r6, r6, ror r5 @ C: ROR #!0
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b .data_arm_apply_r6_and_rn
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mov r6, r6, rrx @ D: RRX
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b .data_arm_apply_r6_and_rn
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b .data_unknown @ E: MUL?
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nop
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b .data_unknown @ F: MUL?
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.data_thumb_abort:
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ldrh r8, [r2] @ read instruction
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tst r8, #1 << 11 @ L = 1 -> write?
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orreq r1, r1, #1 << 8 @ yes
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and r7, r8, #15 << 12
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add pc, pc, r7, lsr #10 @ lookup in table
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nop
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/* 0 */ b .data_unknown
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/* 1 */ b .data_unknown
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/* 2 */ b .data_unknown
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/* 3 */ b .data_unknown
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/* 4 */ b .data_unknown
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/* 5 */ b .data_thumb_reg
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/* 6 */ mov pc, lr
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/* 7 */ mov pc, lr
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/* 8 */ mov pc, lr
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/* 9 */ mov pc, lr
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/* A */ b .data_unknown
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/* B */ b .data_thumb_pushpop
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/* C */ b .data_thumb_ldmstm
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/* D */ b .data_unknown
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/* E */ b .data_unknown
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/* F */ b .data_unknown
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.data_thumb_reg:
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tst r8, #1 << 9
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moveq pc, lr
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tst r8, #1 << 10 @ If 'S' (signed) bit is set
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movne r1, #0 @ it must be a load instr
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mov pc, lr
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.data_thumb_pushpop:
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tst r8, #1 << 10
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beq .data_unknown
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and r6, r8, #0x55 @ hweight8(r8) + R bit
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and r2, r8, #0xaa
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add r6, r6, r2, lsr #1
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and r2, r6, #0xcc
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and r6, r6, #0x33
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add r6, r6, r2, lsr #2
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movs r7, r8, lsr #9 @ C = r8 bit 8 (R bit)
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adc r6, r6, r6, lsr #4 @ high + low nibble + R bit
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and r6, r6, #15 @ number of regs to transfer
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ldr r7, [sp, #13 << 2]
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tst r8, #1 << 11
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addeq r7, r7, r6, lsl #2 @ increment SP if PUSH
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subne r7, r7, r6, lsl #2 @ decrement SP if POP
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str r7, [sp, #13 << 2]
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mov pc, lr
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.data_thumb_ldmstm:
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and r6, r8, #0x55 @ hweight8(r8)
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and r2, r8, #0xaa
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add r6, r6, r2, lsr #1
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and r2, r6, #0xcc
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and r6, r6, #0x33
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add r6, r6, r2, lsr #2
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add r6, r6, r6, lsr #4
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and r5, r8, #7 << 8
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ldr r7, [sp, r5, lsr #6]
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and r6, r6, #15 @ number of regs to transfer
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sub r7, r7, r6, lsl #2 @ always decrement
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str r7, [sp, r5, lsr #6]
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mov pc, lr
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