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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1d328606c6
The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one core to go into this mode before other core. The coupled cpuidle framework can help to sync the MPCore to coupled state then go into "powered-down" idle mode together. The driver can just assume the MPCore come into "powered-down" mode at the same time. No need to take care if the CPU_0 goes into this mode along and only can put it into safe idle mode (WFI). The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI for waiting CPU0 in the same state. When the CPU0 requests powered-down state, it attempts to put the secondary CPU into reset to prevent it from waking up. Then power down both CPUs together and power off the cpu rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
278 lines
6.6 KiB
ArmAsm
278 lines
6.6 KiB
ArmAsm
/*
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* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
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* Copyright (c) 2011, Google, Inc.
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*
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* Author: Colin Cross <ccross@android.com>
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* Gary King <gking@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/proc-fns.h>
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#include <asm/cp15.h>
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#include "sleep.h"
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#include "flowctrl.h"
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#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
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/*
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* tegra20_hotplug_shutdown(void)
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*
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* puts the current cpu in reset
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* should never return
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*/
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ENTRY(tegra20_hotplug_shutdown)
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/* Put this CPU down */
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cpu_id r0
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bl tegra20_cpu_shutdown
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mov pc, lr @ should never get here
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ENDPROC(tegra20_hotplug_shutdown)
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/*
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* tegra20_cpu_shutdown(int cpu)
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*
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* r0 is cpu to reset
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*
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* puts the specified CPU in wait-for-event mode on the flow controller
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* and puts the CPU in reset
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* can be called on the current cpu or another cpu
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* if called on the current cpu, does not return
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* MUST NOT BE CALLED FOR CPU 0.
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*
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* corrupts r0-r3, r12
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*/
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ENTRY(tegra20_cpu_shutdown)
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cmp r0, #0
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moveq pc, lr @ must not be called for CPU 0
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mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
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mov r12, #CPU_RESETTABLE
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str r12, [r1]
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cpu_to_halt_reg r1, r0
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ldr r3, =TEGRA_FLOW_CTRL_VIRT
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mov r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME
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str r2, [r3, r1] @ put flow controller in wait event mode
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ldr r2, [r3, r1]
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isb
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dsb
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movw r1, 0x1011
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mov r1, r1, lsl r0
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ldr r3, =TEGRA_CLK_RESET_VIRT
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str r1, [r3, #0x340] @ put slave CPU in reset
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isb
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dsb
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cpu_id r3
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cmp r3, r0
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beq .
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mov pc, lr
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ENDPROC(tegra20_cpu_shutdown)
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#endif
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#ifdef CONFIG_PM_SLEEP
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/*
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* tegra_pen_lock
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*
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* spinlock implementation with no atomic test-and-set and no coherence
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* using Peterson's algorithm on strongly-ordered registers
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* used to synchronize a cpu waking up from wfi with entering lp2 on idle
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*
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* The reference link of Peterson's algorithm:
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* http://en.wikipedia.org/wiki/Peterson's_algorithm
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*
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* SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
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* on cpu 0:
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* r2 = flag[0] (in SCRATCH38)
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* r3 = flag[1] (in SCRATCH39)
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* on cpu1:
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* r2 = flag[1] (in SCRATCH39)
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* r3 = flag[0] (in SCRATCH38)
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*
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* must be called with MMU on
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* corrupts r0-r3, r12
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*/
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ENTRY(tegra_pen_lock)
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mov32 r3, TEGRA_PMC_VIRT
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cpu_id r0
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add r1, r3, #PMC_SCRATCH37
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cmp r0, #0
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addeq r2, r3, #PMC_SCRATCH38
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addeq r3, r3, #PMC_SCRATCH39
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addne r2, r3, #PMC_SCRATCH39
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addne r3, r3, #PMC_SCRATCH38
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mov r12, #1
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str r12, [r2] @ flag[cpu] = 1
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dsb
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str r12, [r1] @ !turn = cpu
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1: dsb
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ldr r12, [r3]
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cmp r12, #1 @ flag[!cpu] == 1?
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ldreq r12, [r1]
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cmpeq r12, r0 @ !turn == cpu?
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beq 1b @ while !turn == cpu && flag[!cpu] == 1
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mov pc, lr @ locked
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ENDPROC(tegra_pen_lock)
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ENTRY(tegra_pen_unlock)
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dsb
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mov32 r3, TEGRA_PMC_VIRT
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cpu_id r0
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cmp r0, #0
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addeq r2, r3, #PMC_SCRATCH38
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addne r2, r3, #PMC_SCRATCH39
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mov r12, #0
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str r12, [r2]
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mov pc, lr
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ENDPROC(tegra_pen_unlock)
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/*
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* tegra20_cpu_clear_resettable(void)
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*
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* Called to clear the "resettable soon" flag in PMC_SCRATCH41 when
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* it is expected that the secondary CPU will be idle soon.
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*/
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ENTRY(tegra20_cpu_clear_resettable)
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mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
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mov r12, #CPU_NOT_RESETTABLE
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str r12, [r1]
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mov pc, lr
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ENDPROC(tegra20_cpu_clear_resettable)
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/*
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* tegra20_cpu_set_resettable_soon(void)
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*
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* Called to set the "resettable soon" flag in PMC_SCRATCH41 when
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* it is expected that the secondary CPU will be idle soon.
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*/
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ENTRY(tegra20_cpu_set_resettable_soon)
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mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
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mov r12, #CPU_RESETTABLE_SOON
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str r12, [r1]
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mov pc, lr
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ENDPROC(tegra20_cpu_set_resettable_soon)
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/*
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* tegra20_cpu_is_resettable_soon(void)
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*
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* Returns true if the "resettable soon" flag in PMC_SCRATCH41 has been
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* set because it is expected that the secondary CPU will be idle soon.
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*/
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ENTRY(tegra20_cpu_is_resettable_soon)
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mov32 r1, TEGRA_PMC_VIRT + PMC_SCRATCH41
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ldr r12, [r1]
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cmp r12, #CPU_RESETTABLE_SOON
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moveq r0, #1
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movne r0, #0
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mov pc, lr
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ENDPROC(tegra20_cpu_is_resettable_soon)
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/*
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* tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
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*
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* Enters WFI on secondary CPU by exiting coherency.
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*/
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ENTRY(tegra20_sleep_cpu_secondary_finish)
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stmfd sp!, {r4-r11, lr}
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mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency
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/* Flush and disable the L1 data cache */
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bl tegra_disable_clean_inv_dcache
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mov32 r0, TEGRA_PMC_VIRT + PMC_SCRATCH41
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mov r3, #CPU_RESETTABLE
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str r3, [r0]
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bl cpu_do_idle
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/*
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* cpu may be reset while in wfi, which will return through
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* tegra_resume to cpu_resume
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* or interrupt may wake wfi, which will return here
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* cpu state is unchanged - MMU is on, cache is on, coherency
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* is off, and the data cache is off
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*
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* r11 contains the original actlr
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*/
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bl tegra_pen_lock
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mov32 r3, TEGRA_PMC_VIRT
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add r0, r3, #PMC_SCRATCH41
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mov r3, #CPU_NOT_RESETTABLE
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str r3, [r0]
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bl tegra_pen_unlock
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/* Re-enable the data cache */
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mrc p15, 0, r10, c1, c0, 0
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orr r10, r10, #CR_C
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mcr p15, 0, r10, c1, c0, 0
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isb
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mcr p15, 0, r11, c1, c0, 1 @ reenable coherency
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/* Invalidate the TLBs & BTAC */
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mov r1, #0
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mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs
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mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
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dsb
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isb
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/* the cpu was running with coherency disabled,
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* caches may be out of date */
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bl v7_flush_kern_cache_louis
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ldmfd sp!, {r4 - r11, pc}
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ENDPROC(tegra20_sleep_cpu_secondary_finish)
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/*
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* tegra20_tear_down_cpu
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*
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* Switches the CPU cluster to PLL-P and enters sleep.
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*/
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ENTRY(tegra20_tear_down_cpu)
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bl tegra_switch_cpu_to_pllp
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b tegra20_enter_sleep
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ENDPROC(tegra20_tear_down_cpu)
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/*
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* tegra20_enter_sleep
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*
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* uses flow controller to enter sleep state
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* executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
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* executes from SDRAM with target state is LP2
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*/
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tegra20_enter_sleep:
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mov32 r6, TEGRA_FLOW_CTRL_BASE
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mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
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orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
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cpu_id r1
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cpu_to_halt_reg r1, r1
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str r0, [r6, r1]
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dsb
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ldr r0, [r6, r1] /* memory barrier */
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halted:
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dsb
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wfe /* CPU should be power gated here */
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isb
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b halted
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#endif
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