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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4a9e5ca1a5
The phy_ops variables are never modified after initialized in these drivers, so make them const. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
217 lines
5.6 KiB
C
217 lines
5.6 KiB
C
/*
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* Broadcom SATA3 AHCI Controller PHY Driver
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*
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* Copyright © 2009-2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#define SATA_MDIO_BANK_OFFSET 0x23c
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#define SATA_MDIO_REG_OFFSET(ofs) ((ofs) * 4)
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#define SATA_MDIO_REG_SPACE_SIZE 0x1000
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#define SATA_MDIO_REG_LENGTH 0x1f00
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#define MAX_PORTS 2
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/* Register offset between PHYs in PCB space */
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#define SATA_MDIO_REG_SPACE_SIZE 0x1000
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struct brcm_sata_port {
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int portnum;
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struct phy *phy;
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struct brcm_sata_phy *phy_priv;
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bool ssc_en;
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};
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struct brcm_sata_phy {
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struct device *dev;
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void __iomem *phy_base;
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struct brcm_sata_port phys[MAX_PORTS];
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};
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enum sata_mdio_phy_regs_28nm {
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PLL_REG_BANK_0 = 0x50,
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PLL_REG_BANK_0_PLLCONTROL_0 = 0x81,
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TXPMD_REG_BANK = 0x1a0,
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TXPMD_CONTROL1 = 0x81,
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TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0),
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TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = BIT(1),
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TXPMD_TX_FREQ_CTRL_CONTROL1 = 0x82,
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TXPMD_TX_FREQ_CTRL_CONTROL2 = 0x83,
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TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff,
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TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84,
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TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff,
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};
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static inline void __iomem *brcm_sata_phy_base(struct brcm_sata_port *port)
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{
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struct brcm_sata_phy *priv = port->phy_priv;
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return priv->phy_base + (port->portnum * SATA_MDIO_REG_SPACE_SIZE);
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}
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static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
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u32 msk, u32 value)
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{
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u32 tmp;
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writel(bank, addr + SATA_MDIO_BANK_OFFSET);
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tmp = readl(addr + SATA_MDIO_REG_OFFSET(ofs));
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tmp = (tmp & msk) | value;
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writel(tmp, addr + SATA_MDIO_REG_OFFSET(ofs));
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}
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/* These defaults were characterized by H/W group */
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#define FMIN_VAL_DEFAULT 0x3df
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#define FMAX_VAL_DEFAULT 0x3df
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#define FMAX_VAL_SSC 0x83
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static void brcm_sata_cfg_ssc_28nm(struct brcm_sata_port *port)
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{
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void __iomem *base = brcm_sata_phy_base(port);
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struct brcm_sata_phy *priv = port->phy_priv;
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u32 tmp;
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/* override the TX spread spectrum setting */
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tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
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brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
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/* set fixed min freq */
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brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
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~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
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FMIN_VAL_DEFAULT);
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/* set fixed max freq depending on SSC config */
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if (port->ssc_en) {
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dev_info(priv->dev, "enabling SSC on port %d\n", port->portnum);
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tmp = FMAX_VAL_SSC;
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} else {
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tmp = FMAX_VAL_DEFAULT;
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}
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brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
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~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
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}
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static int brcm_sata_phy_init(struct phy *phy)
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{
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struct brcm_sata_port *port = phy_get_drvdata(phy);
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brcm_sata_cfg_ssc_28nm(port);
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return 0;
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}
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static const struct phy_ops phy_ops_28nm = {
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.init = brcm_sata_phy_init,
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.owner = THIS_MODULE,
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};
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static const struct of_device_id brcm_sata_phy_of_match[] = {
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{ .compatible = "brcm,bcm7445-sata-phy" },
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{},
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};
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MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
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static int brcm_sata_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *dn = dev->of_node, *child;
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struct brcm_sata_phy *priv;
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struct resource *res;
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struct phy_provider *provider;
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int count = 0;
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if (of_get_child_count(dn) == 0)
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return -ENODEV;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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dev_set_drvdata(dev, priv);
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priv->dev = dev;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
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priv->phy_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->phy_base))
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return PTR_ERR(priv->phy_base);
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for_each_available_child_of_node(dn, child) {
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unsigned int id;
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struct brcm_sata_port *port;
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if (of_property_read_u32(child, "reg", &id)) {
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dev_err(dev, "missing reg property in node %s\n",
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child->name);
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return -EINVAL;
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}
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if (id >= MAX_PORTS) {
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dev_err(dev, "invalid reg: %u\n", id);
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return -EINVAL;
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}
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if (priv->phys[id].phy) {
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dev_err(dev, "already registered port %u\n", id);
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return -EINVAL;
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}
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port = &priv->phys[id];
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port->portnum = id;
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port->phy_priv = priv;
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port->phy = devm_phy_create(dev, child, &phy_ops_28nm);
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port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
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if (IS_ERR(port->phy)) {
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dev_err(dev, "failed to create PHY\n");
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return PTR_ERR(port->phy);
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}
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phy_set_drvdata(port->phy, port);
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count++;
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}
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provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(provider)) {
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dev_err(dev, "could not register PHY provider\n");
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return PTR_ERR(provider);
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}
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dev_info(dev, "registered %d port(s)\n", count);
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return 0;
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}
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static struct platform_driver brcm_sata_phy_driver = {
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.probe = brcm_sata_phy_probe,
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.driver = {
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.of_match_table = brcm_sata_phy_of_match,
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.name = "brcmstb-sata-phy",
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}
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};
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module_platform_driver(brcm_sata_phy_driver);
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MODULE_DESCRIPTION("Broadcom STB SATA PHY driver");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Marc Carino");
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MODULE_AUTHOR("Brian Norris");
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MODULE_ALIAS("platform:phy-brcmstb-sata");
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