mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 20:36:45 +07:00
be4ea89c8d
Make falcon_spi_wait() ignore the write timer - it is only relevant to write commands, it only works for the device that contains VPD, and it might not be initialised properly at all. Rename falcon_spi_fast_wait() to falcon_spi_wait_write(), reflecting its use, and make it wait up to 10 ms (not 1 ms) since buffered writes to EEPROM may take this long to complete. Make both wait functions sleep instead of busy-waiting. Replace wait for command completion at top of falcon_spi_cmd() with a single poll; no command should be running when the function starts. Correct some comments. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
97 lines
3.7 KiB
C
97 lines
3.7 KiB
C
/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2005 Fen Systems Ltd.
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* Copyright 2006 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#ifndef EFX_SPI_H
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#define EFX_SPI_H
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#include "net_driver.h"
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/**************************************************************************
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*
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* Basic SPI command set and bit definitions
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*
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*************************************************************************/
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#define SPI_WRSR 0x01 /* Write status register */
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#define SPI_WRITE 0x02 /* Write data to memory array */
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#define SPI_READ 0x03 /* Read data from memory array */
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#define SPI_WRDI 0x04 /* Reset write enable latch */
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#define SPI_RDSR 0x05 /* Read status register */
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#define SPI_WREN 0x06 /* Set write enable latch */
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#define SPI_SST_EWSR 0x50 /* SST: Enable write to status register */
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#define SPI_STATUS_WPEN 0x80 /* Write-protect pin enabled */
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#define SPI_STATUS_BP2 0x10 /* Block protection bit 2 */
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#define SPI_STATUS_BP1 0x08 /* Block protection bit 1 */
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#define SPI_STATUS_BP0 0x04 /* Block protection bit 0 */
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#define SPI_STATUS_WEN 0x02 /* State of the write enable latch */
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#define SPI_STATUS_NRDY 0x01 /* Device busy flag */
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/**
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* struct efx_spi_device - an Efx SPI (Serial Peripheral Interface) device
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* @efx: The Efx controller that owns this device
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* @mtd: MTD state
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* @device_id: Controller's id for the device
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* @size: Size (in bytes)
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* @addr_len: Number of address bytes in read/write commands
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* @munge_address: Flag whether addresses should be munged.
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* Some devices with 9-bit addresses (e.g. AT25040A EEPROM)
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* use bit 3 of the command byte as address bit A8, rather
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* than having a two-byte address. If this flag is set, then
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* commands should be munged in this way.
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* @erase_command: Erase command (or 0 if sector erase not needed).
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* @erase_size: Erase sector size (in bytes)
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* Erase commands affect sectors with this size and alignment.
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* This must be a power of two.
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* @block_size: Write block size (in bytes).
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* Write commands are limited to blocks with this size and alignment.
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*/
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struct efx_spi_device {
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struct efx_nic *efx;
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#ifdef CONFIG_SFC_MTD
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void *mtd;
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#endif
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int device_id;
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unsigned int size;
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unsigned int addr_len;
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unsigned int munge_address:1;
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u8 erase_command;
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unsigned int erase_size;
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unsigned int block_size;
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};
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int falcon_spi_cmd(const struct efx_spi_device *spi, unsigned int command,
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int address, const void* in, void *out, size_t len);
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int falcon_spi_wait_write(const struct efx_spi_device *spi);
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int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
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size_t len, size_t *retlen, u8 *buffer);
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int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
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size_t len, size_t *retlen, const u8 *buffer);
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/*
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* SFC4000 flash is partitioned into:
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* 0-0x400 chip and board config (see falcon_hwdefs.h)
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* 0x400-0x8000 unused (or may contain VPD if EEPROM not present)
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* 0x8000-end boot code (mapped to PCI expansion ROM)
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* SFC4000 small EEPROM (size < 0x400) is used for VPD only.
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* SFC4000 large EEPROM (size >= 0x400) is partitioned into:
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* 0-0x400 chip and board config
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* configurable VPD
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* 0x800-0x1800 boot config
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* Aside from the chip and board config, all of these are optional and may
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* be absent or truncated depending on the devices used.
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*/
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#define FALCON_NVCONFIG_END 0x400U
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#define FALCON_FLASH_BOOTCODE_START 0x8000U
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#define EFX_EEPROM_BOOTCONFIG_START 0x800U
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#define EFX_EEPROM_BOOTCONFIG_END 0x1800U
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#endif /* EFX_SPI_H */
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