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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 09:26:58 +07:00
f41507245e
The boot code that appears as a PCI expansion ROM on the SFC4000 is stored in flash. Expose this as a standard MTD device to allow for in-place upgrades. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
84 lines
2.9 KiB
C
84 lines
2.9 KiB
C
/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2005-2006 Fen Systems Ltd.
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* Copyright 2006-2008 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#ifndef EFX_EFX_H
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#define EFX_EFX_H
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#include "net_driver.h"
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/* PCI IDs */
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#define EFX_VENDID_SFC 0x1924
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#define FALCON_A_P_DEVID 0x0703
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#define FALCON_A_S_DEVID 0x6703
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#define FALCON_B_P_DEVID 0x0710
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/* TX */
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extern int efx_xmit(struct efx_nic *efx,
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struct efx_tx_queue *tx_queue, struct sk_buff *skb);
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extern void efx_stop_queue(struct efx_nic *efx);
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extern void efx_wake_queue(struct efx_nic *efx);
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/* RX */
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extern void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index);
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extern void efx_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index,
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unsigned int len, bool checksummed, bool discard);
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extern void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay);
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/* Channels */
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extern void efx_process_channel_now(struct efx_channel *channel);
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extern void efx_flush_queues(struct efx_nic *efx);
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/* Ports */
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extern void efx_reconfigure_port(struct efx_nic *efx);
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extern void __efx_reconfigure_port(struct efx_nic *efx);
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/* Reset handling */
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extern void efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd);
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extern int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd,
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bool ok);
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/* Global */
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extern void efx_schedule_reset(struct efx_nic *efx, enum reset_type type);
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extern void efx_suspend(struct efx_nic *efx);
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extern void efx_resume(struct efx_nic *efx);
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extern void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs,
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int rx_usecs);
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extern int efx_request_power(struct efx_nic *efx, int mw, const char *name);
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extern void efx_hex_dump(const u8 *, unsigned int, const char *);
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/* Dummy PHY ops for PHY drivers */
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extern int efx_port_dummy_op_int(struct efx_nic *efx);
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extern void efx_port_dummy_op_void(struct efx_nic *efx);
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extern void efx_port_dummy_op_blink(struct efx_nic *efx, bool blink);
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/* MTD */
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#ifdef CONFIG_SFC_MTD
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extern int efx_mtd_probe(struct efx_nic *efx);
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extern void efx_mtd_rename(struct efx_nic *efx);
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extern void efx_mtd_remove(struct efx_nic *efx);
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#else
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static inline int efx_mtd_probe(struct efx_nic *efx) { return 0; }
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static inline void efx_mtd_rename(struct efx_nic *efx) {}
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static inline void efx_mtd_remove(struct efx_nic *efx) {}
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#endif
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extern unsigned int efx_monitor_interval;
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static inline void efx_schedule_channel(struct efx_channel *channel)
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{
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EFX_TRACE(channel->efx, "channel %d scheduling NAPI poll on CPU%d\n",
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channel->channel, raw_smp_processor_id());
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channel->work_pending = true;
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netif_rx_schedule(channel->napi_dev, &channel->napi_str);
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}
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#endif /* EFX_EFX_H */
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